Inverter Ring Phase Circuit for Low-Jitter DDR Clock Alignment
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Solution Overview
Problem
Current digital phase generators in DDR SDRAM devices face issues of high power consumption, jitter, and four-phase misalignment during high-speed operation.
Innovation Solution
A digital phase circuit with an inverter ring configuration where alternating inverters operate in high impedance and normal modes to function as a frequency divider, reducing jitter and phase misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog circuit is used to generate four-phase clock signals, then the clock signal generation is reliable, but power consumption increases
Solution Approach 1:
The patent replaces the analog circuit system with a digital circuit system. Specifically, it uses a digital phase generator comprising an inverter ring oscillator and phase alignment circuits to generate four-phase clock signals, substituting the traditional analog approach with a digital implementation that achieves both low power consumption and high reliability
Solution Approach 2:
The patent changes the operating parameters of the inverter ring by introducing high-impedance states to specific inverters (first and third inverters) while keeping others in normal operation mode. This parameter change enables the ring to function as a frequency divider, improving power efficiency while maintaining signal integrity
2Use of energy by moving object
If a traditional digital four-phase generator is used, then power consumption is reduced, but jitter and phase misalignment occur during high-speed operation
Solution Approach 1:
The patent segments the inverter ring into different functional groups: first and third inverters operate in high-impedance mode while second and fourth inverters operate in normal mode. This segmentation allows the circuit to function as a frequency divider, reducing jitter and phase misalignment while maintaining low power consumption
Solution Approach 2:
The patent introduces phase alignment circuits that use feedback mechanisms to detect and correct phase misalignment between clock signals. The feedback ensures that even during high-speed operation, the four-phase clock signals maintain proper alignment and stability
Data Source
AI summary
A digital phase circuit is provided. The digital phase circuit includes a first inverter to a fourth inverter. The first inverter to the fourth inverter are connected in series to form an inverter ring, wherein an output end of the first inverter provides a first clock signal, an output end of the second inverter provides a second clock signal, an output end of the third inverter provides a third clock signal, and an output end of the fourth inverter provides a fourth clock signal. In particular, the first inverter and the third inverter are operated in one of a high impedance mode and a normal mode. At the same time, the second inverter and the fourth inverter are operated in the other of the high impedance mode and the normal mode.