Inverter-Based SAR CDC With Coarse-Fine CapDAC for Low-Power Resolution
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Solution Overview
Problem
Conventional capacitance-to-digital converters (CDCs) face challenges with energy efficiency, suffering from signal-dependent conversion errors, parasitic dependency, and poor resolution, particularly in wireless sensor nodes and implantable biomedical sensors, where minimizing energy consumption is crucial.
Innovation Solution
An inverter-based successive approximation register (SAR) CDC architecture that uses inverter-based amplifiers to overcome offset-induced errors and parasitic dependency, achieving reduced power consumption while maintaining robust operation and improved energy efficiency, with a coarse-fine capacitive digital-to-analog converter (CapDAC) for enhanced resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CDC architectures are used, then conversion functionality is provided, but energy consumption is high and resolution is poor
Solution Approach 1:
The patent extracts and eliminates power-hungry operational amplifiers from the CDC architecture, replacing them with inverter-based circuits. This removal of the harmful power-consuming component directly addresses the contradiction by reducing energy consumption while maintaining conversion functionality through the inverter-based successive approximation register approach
Solution Approach 2:
The patent substitutes traditional analog operational amplifier-based conversion mechanisms with digital inverter-based successive approximation circuits. This replacement transitions from a power-intensive analog mechanism to a more energy-efficient digital mechanism, resolving the contradiction between conversion precision and energy consumption
2Ease of operation
If operational amplifiers are used in CDC, then conversion is performed, but power consumption increases and energy efficiency degrades
Solution Approach 1:
The patent removes operational amplifiers from the CDC circuit architecture, eliminating their associated power consumption. The inverter-based circuits perform the same conversion operation without the energy loss inherent in op-amp-based designs, directly addressing the contradiction between operational capability and energy efficiency
Solution Approach 2:
The patent changes the fundamental operating parameters of the CDC by transitioning from analog op-amp operation to digital inverter operation. This parameter change enables the same conversion function to be performed with significantly reduced power consumption, resolving the contradiction between ease of operation and energy loss
3Device complexity
If simple SAR CDC is used, then circuit complexity is reduced, but conversion errors increase due to comparator offset voltage sensitivity
Solution Approach 1:
The patent introduces inverter-based amplifier circuits as intermediary stages between the capacitive sensor and the comparator. These intermediary inverters amplify the differential voltage signal before comparison, making the conversion process less sensitive to comparator offset voltage while maintaining relatively simple circuit architecture
Solution Approach 2:
The patent performs preliminary signal amplification using inverter-based circuits before the comparison stage. This preliminary action prepares the signal in advance to be more robust against comparator offset errors, resolving the contradiction between circuit simplicity and conversion reliability
Data Source
AI summary
An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog-to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter-based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.


