Inverter Shutoff Circuit with Microprocessor Feedback Monitoring

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Solution Overview

Problem

Inverters face challenges in meeting stringent ASIL-D requirements due to potential single point or latent point failures in safety logic and shutoff circuits, leading to unintended transitions into safe states like Active Short Circuit (ASC) or Free Wheeling (FW) modes, which are not intended operations and can abruptly turn off motors.

Innovation Solution

A safety mechanism with minimal additional hardware is implemented, utilizing a microprocessor to monitor feedback signals from buffers and enable ASC or FW modes based on motor speed thresholds, with resistors providing feedback signals to detect faults and prevent unintended safe state transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant hardware circuits are used to meet ASIL-D requirements, then reliability is improved, but device complexity increases

Engineering Contradiction:
ImproveASIL-D complianceVSAvoidhardware circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces redundant hardware safety circuits with a microprocessor-based software monitoring system. The microprocessor continuously monitors feedback signals from buffers and implements safety logic through software, eliminating the need for complex hardware-based redundant safety circuits while achieving ASIL-D functional safety requirements

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system uses the existing control board resources (microprocessor, buffers, feedback signal paths) to perform safety monitoring functions. The microprocessor leverages the existing PWM signal paths and buffer outputs to generate feedback signals for safety monitoring, eliminating the need for separate dedicated safety monitoring hardware

Inventive Principle:
Principle #25Self-service

2Device complexity

If software-based safe state management is used, then device complexity is reduced, but reliability may worsen due to potential software failures

Engineering Contradiction:
Improvecircuit complexityVSAvoidfunctional safety
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system implements continuous feedback monitoring where the microprocessor reads feedback signals from the buffers that reflect the actual state of PWM outputs. This closed-loop feedback mechanism allows the software to detect unintended safe state transitions and take corrective action, ensuring functional safety through continuous verification of system state

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The software is configured with predefined safety logic and response protocols before operation. When specific feedback signal patterns indicate potential failures or unintended safe state transitions, the pre-programmed safety routines automatically execute appropriate corrective actions, ensuring reliable safe state management without requiring complex runtime decision-making

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4156485A1Systems and methods for controlling inverter having shutoff circuit
Publication Date: 2023.03.29 BORGWARNER US TECHNOLOGIES LLC
  • EP4156485A1 patent drawingFigure 1
  • EP4156485A1 patent drawingFigure 2
  • EP4156485A1 patent drawingFigure 3

AI summary

A system includes a control board comprising: a microprocessor configured to output a PWM signal; a primary shutoff path circuit, an upper MOSFET shutoff circuit, and a lower MOSFET shutoff circuit, each of the circuits configured to receive the PWM signal; a first buffer provided at an output of the primary shutoff path circuit; a second buffer provided at an output of the upper MOSFET shutoff circuit; a third buffer provided at an output of the lower MOSFET shutoff circuit; a first resistor and a second resistor provided in parallel at the first buffer and configured to provide a first feedback signal; a third resistor and a fourth resistor provided in parallel at the second buffer and configured to provide a second feedback signal; and a fifth resistor and a sixth resistor provided in parallel at the third buffer and configured to provide a third feedback signal.