Inverter-Based Threshold Verification for Multi-Level Cell NVM
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Solution Overview
Problem
Conventional Multi-Level Cell (MLC) Non-Volatile Memory (NVM) technologies face challenges in increasing the number of resolvable threshold voltage levels due to non-uniformity in programming conditions and fabrication variations, limiting the bit capacity per cell.
Innovation Solution
An inverter-type verification circuit is used to detect and adjust threshold voltages of NVM cells within a desired window by applying a level verification input voltage and fine-tuning the programming sequence, allowing more threshold voltage levels to fit within a limited range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional reference cell scheme is used for verification, then verification process is simple, but threshold voltage distribution width cannot be controlled to desired accuracy
Solution Approach 1:
The patent inverts the conventional verification approach by using an NVM inverter circuit instead of a reference cell. The inverter's output voltage characteristics are exploited to verify threshold voltages, where the inverter naturally amplifies voltage differences and provides a more sensitive verification mechanism that achieves desired accuracy without requiring complex reference cell arrays.
Solution Approach 2:
The NVM inverter acts as an intermediary device between the threshold voltage to be verified and the verification read circuit. The inverter converts small threshold voltage variations into larger output voltage changes, serving as a mediator that enhances the verification signal and enables more precise measurement of threshold voltage distribution.
2Quantity of substance
If number of threshold voltage levels is increased to improve bit capacity, then bit capacity per cell increases, but threshold voltage distribution becomes non-uniform and harder to resolve
Solution Approach 1:
The patent applies preliminary fine-tuning programming sequences before final verification to pre-adjust threshold voltages into the desired distribution window. This preliminary action ensures that threshold voltages are positioned correctly before the verification process, preventing non-uniformity from developing and enabling higher bit capacity with maintained precision.
Solution Approach 2:
The verification process provides feedback on the actual threshold voltage distribution, which is then used to adjust subsequent programming operations. This feedback loop allows the system to compensate for non-uniformity and maintain precise threshold voltage control even as the number of levels increases to enhance bit capacity.
3Measurement precision
If fine-tuning programming sequence is applied to adjust all threshold voltages into desired window, then threshold voltage distribution accuracy improves, but programming time increases
Solution Approach 1:
The patent applies fine-tuning programming selectively only to cells that fall outside the desired threshold voltage window, rather than re-programming all cells. This partial action approach maintains high accuracy for cells needing adjustment while avoiding unnecessary programming operations on cells already within specifications, thereby reducing overall programming time.
Solution Approach 2:
The programming process is segmented into multiple phases: initial fast programming to establish rough threshold voltage levels, followed by verification, and then selective fine-tuning only for cells that fail verification. This segmentation allows the system to achieve high accuracy through fine-tuning while minimizing the time impact by limiting fine-tuning to only the necessary subset of cells.
Data Source
AI summary
Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy.