Clock Gating Circuit Without Inverters for Lower Disabled Power
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Solution Overview
Problem
Conventional clock gating cells consume significant power even when not enabled due to 50% of their transistors toggling with the clock signal, leading to substantial power consumption in micro-chips.
Innovation Solution
A clock gating circuit design that reduces the number of transistors toggling with the clock signal by eliminating the need for inverters to generate out-of-phase clock signals, resulting in a circuit with only 5 transistors toggling when disabled, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock gating cells use inverters to generate out-of-phase clock signals, then the clock signal can be properly distributed to all blocks, but 50% of transistors will toggle even when disabled, causing significant power consumption
Solution Approach 1:
The patent removes the inverter stage from the clock gating cell, extracting the source of unnecessary transistor toggling. By eliminating the inverter that generates out-of-phase clock signals, the design prevents 50% of transistors from toggling when disabled, directly reducing power consumption while maintaining reliable clock distribution through alternative circuit topology
Solution Approach 2:
The patent implements dynamic control of transistor toggling based on the enable signal state. When the enable signal is low, the circuit dynamically prevents clock signal propagation to the transistor gates, making the transistor switching behavior adaptive to the operational state rather than continuously toggling, thereby reducing dynamic power consumption
2Loss of energy
If clock gating cells are used to save power by gating off clocks to inactive blocks, then dynamic power in the system is reduced, but the clock gating cell itself consumes significant power when disabled
Solution Approach 1:
The patent converts the harmful effect of continuous transistor toggling into a beneficial low-power state by using the enable signal to control transistor gating. The same clock signal that previously caused power consumption is now utilized in a controlled manner where transistors are gated off when not needed, transforming the power consumption problem into a power saving solution
Solution Approach 2:
The patent changes the operational parameters of the transistors by controlling their gate voltages through the enable signal. When disabled, the transistors are biased to remain in cutoff or triode region rather than switching, changing their electrical state from active toggling to passive conduction, thereby reducing power consumption while maintaining circuit functionality
3Speed
If 50% of transistors toggle with the clock signal even when disabled, then the clock gating cell can maintain readiness for quick activation, but power consumption increases significantly across micro-chip
Solution Approach 1:
The patent prepares the circuit for quick activation by maintaining the enable signal control mechanism in a ready state. The transistors are pre-configured through the enable signal logic to be rapidly activated when needed, without requiring continuous toggling. The circuit topology is preliminarily arranged to allow fast response while minimizing idle power consumption
Data Source
AI summary
A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.