Invertible Logic Gate Circuit Escaping Local Minima

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Solution Overview

Problem

Invertible logic gates in processing circuits often get stuck in local minimum energy states, preventing them from transitioning to global minimum energy states, which are the true calculation results.

Innovation Solution

A processing circuit formed with a combination of invertible logic gates that probabilistically updates signal values based on a Hamiltonian-defined relationship between input and output nodes, using a first and second evaluation value generation function, and a node data update function to ensure signal values converge to a valid state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If invertible logic gates are used to solve inverse problems, then the calculation can proceed through time evolution, but the signal values may get trapped in local minimum energy states and fail to reach the global minimum energy state

Engineering Contradiction:
Improveconvergence to correct solutionVSAvoidtime evolution duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the Hamiltonian time-dependent through a scheduling mechanism. The Hamiltonian transitions from an initial configuration to a final configuration over time, allowing the system to evolve dynamically. This time-varying Hamiltonian enables the system to escape local minima by continuously changing the energy landscape, thereby improving convergence reliability while managing time evolution duration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes parameters by modifying the Hamiltonian function over time. The scheduling unit adjusts the Hamiltonian parameters from initial values to final values in a controlled manner. This parameter change strategy allows the system to transition smoothly through different energy states, preventing trapping in local minima and ensuring convergence to the global minimum energy state.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If the Hamiltonian is fixed, then the energy state remains stable, but the system cannot escape local minimum energy states to reach the global minimum

Engineering Contradiction:
Improveenergy state stabilityVSAvoidtransition to correct solution
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent resolves this contradiction by making the Hamiltonian dynamic rather than fixed. The scheduling unit continuously adjusts the Hamiltonian parameters during time evolution, creating a time-varying energy landscape. This dynamic approach maintains temporary stability at each time step while enabling global transitions, allowing the system to escape local minima and reach the global minimum energy state reliably.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies periodic action through the scheduled evolution of the Hamiltonian. The system undergoes periodic updates to the Hamiltonian parameters, creating a rhythm of stabilization and transition. This periodic modulation of the energy landscape enables the system to systematically explore different states and eventually converge to the correct solution while maintaining stability during each evolution phase.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20230409288A1Processing circuit, logic gate, arithmetic processing method, and non-transitory computer-readable storage medium
Publication Date: 2023.12.21 CANON KK
  • US20230409288A1 patent drawing
  • US20230409288A1 patent drawing
  • US20230409288A1 patent drawing

AI summary

A processing circuit according to an embodiment includes a plurality of logic gates in combination each of which is configured to probabilistically determine, based on signal values of one or two or more input nodes and output nodes at a certain time, signal values at at least one of the input nodes and the output nodes at a subsequent time, in which the processing circuit controls the signal values based on a relationship to be satisfied between at least some nodes of the input nodes and the output nodes.