Inverting Integrated Clock Gate for Clock Network Generation
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Solution Overview
Problem
Conventional clock network generation in circuit design often requires unnecessary inverter stages for polarity fixing, leading to increased cell count, power consumption, and area usage, which can hinder congestion and routability within the circuit.
Innovation Solution
The introduction of inverting integrated clock gates (ICGs) allows for the reduction of inverter stages by swapping non-inverting ICGs with inverting ICGs, thereby reducing the number of inverters and clock wires, and optimizing the clock network topology during clock tree synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional non-inverting ICGs are used for clock network generation, then the clock network can be generated with standard topology, but additional inverter stages are required for polarity fixing which increases cell count, power consumption, and area usage
Solution Approach 1:
The patent applies inversion by switching from conventional non-inverting ICGs to inverting ICGs in the clock network. This fundamental inversion of the clock gate type eliminates the need for additional inverter stages that would otherwise be required for polarity fixing, thereby reducing cell count, power consumption, and area usage while maintaining proper clock signal distribution
2Reliability
If additional inverter stages are added for polarity fixing, then clock signal polarity can be maintained, but cell count and power consumption increase
Solution Approach 1:
By inverting the clock gate type from non-inverting to inverting ICG, the patent eliminates the need for separate inverter stages for polarity fixing. The inverting ICG inherently provides the required polarity transformation as part of its clock gating function, thus maintaining clock signal polarity reliability while eliminating the additional power consumption that would result from extra inverter stages
3Ease of operation
If more inverter stages are used, then clock signal distribution can be achieved, but area usage and congestion increase
Solution Approach 1:
The patent resolves the area and congestion issue by inverting the clock gate type to inverting ICG, which integrates the inversion function directly into the clock gating logic. This eliminates the need for separate inverter stages that would occupy additional circuit area and increase congestion, while still achieving proper clock signal distribution to all required locations
Data Source
AI summary
Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.