Inverting Level-Shifter for Dual-Rail SRAM Signal Delay
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Solution Overview
Problem
The delay in trigger signals to sense amplifiers in integrated memory circuits due to level-shifters and inverters causes performance and power consumption issues, as these components are required to operate between different supply voltage domains, leading to delayed read operations and increased leakage currents.
Innovation Solution
A novel high-speed, low-latency inverting level-shifter is introduced between the self-timing control circuit and the sense amplifier, reducing the number of circuit elements and increasing operating speed to minimize signal delay and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level-shifter and inverter are inserted between self-timing control circuit and sense amplifier to operate between different supply voltage domains, then voltage domain compatibility is achieved, but signal delay increases and read operation speed decreases
Solution Approach 1:
The patent combines the level-shifter and inverter into a single integrated circuit block that performs both voltage level shifting and signal inversion simultaneously. This merging eliminates the need for separate level-shifter and inverter components, thereby reducing the total number of circuit elements and minimizing signal propagation delay while maintaining compatibility between different supply voltage domains (VDD and VDDA)
Solution Approach 2:
The integrated circuit performs multiple functions within a single block: it acts as both a level-shifter (converting signals from VDD domain to VDDA domain) and an inverter (logically inverting the trigger signal). This multi-functionality reduces device complexity and minimizes the number of discrete components required in the signal path between the self-timing control circuit and sense amplifier
2Adaptability or versatility
If level-shifter and inverter are inserted between self-timing control circuit and sense amplifier, then voltage level conversion is enabled, but device complexity increases
Solution Approach 1:
The patent merges the level-shifter and inverter functions into a single integrated circuit block, reducing the number of discrete circuit elements from two separate components to one unified component. This merging directly reduces device complexity while maintaining the necessary voltage level conversion capability between VDD and VDDA domains
Solution Approach 2:
The integrated circuit is designed to perform multiple functions (level shifting and inversion) within a single device structure, thereby reducing overall device complexity. The universal design allows one component to replace what would traditionally require two separate components, simplifying the circuit architecture
3Adaptability or versatility
If traditional level-shifter and inverter configuration is used, then voltage domain adaptation is achieved, but power consumption increases due to leakage currents
Solution Approach 1:
By merging the level-shifter and inverter into a single integrated circuit, the patent reduces the total number of transistor switches and circuit interfaces. Fewer discrete components mean fewer potential leakage paths, thereby reducing overall leakage currents and power consumption while maintaining proper voltage domain adaptation between VDD and VDDA domains
Data Source
AI summary
In one embodiment, a self-timed, dual-rail SRAM includes a self-timing circuit having a logic gate that is powered by voltage VDD and configured to receive a fire-sense-amplifier timing signal and to produce a VDD-domain sense-amplifier-enable signal SOELV. The self-timing circuit includes an inverting level-shifter having complementary N-type and P-type transistors connected in series between voltage VDDA and ground. The N-type transistor's gate is connected to signal SOELV, and both transistors' drain terminals are connected together to produce output signal SOEHVB. The inverting level-shifter also includes two series-connected P-type transistors connected (i) between supply voltage VDDA and the output and (ii) in parallel with the first P-type (pull-up) transistor. An inverter is connected between the output node and the control terminal of one of the series transistors, and the other series-transistor's gate is connected to signal SOELV. Thus, the series transistors provide a rapid latching and latch-breaking function.