I/O Array Test Circuit With Parallel Signal Comparison
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Solution Overview
Problem
As memory density increases, the time required for fully testing memory arrays also increases, and existing data compression techniques can decrease operation speed during normal operations due to data paths overhead.
Innovation Solution
A test circuit for input/output arrays that includes M write drivers and M comparing circuits, with buffers between them, utilizing 2-to-1 and 3-to-1 comparators and AND gates to determine and output comparing results, enabling efficient testing and fault detection across multiple arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data compression circuitry is included in memory to decrease test time, then test time is reduced, but operation speed during normal operations decreases due to data paths overhead
Solution Approach 1:
The invention divides the memory system into separate test mode and normal operation mode pathways. The data compression circuitry is activated only during test mode, while normal operation bypasses this circuitry, thus reducing test time without impacting normal operation speed. This is achieved through mode selection logic that routes operations through appropriate pathways.
Solution Approach 2:
The system dynamically switches between different operational modes (test mode and normal operation mode) to activate or deactivate the data compression circuitry as needed. This dynamic switching ensures that the compression circuitry only consumes resources during testing, not during normal memory operations, thereby maintaining normal operation speed while enabling fast testing.
2Reliability
If data is written into and read from multiple memory cells during testing, then comprehensive testing is achieved, but test time increases with memory density
Solution Approach 1:
The invention merges multiple memory cell testing operations into a single compressed data stream. By reading data from multiple memory cells simultaneously and compressing it through the data compression circuitry, the system achieves comprehensive testing coverage while reducing the time required to transfer and process the test data.
Solution Approach 2:
The system creates compressed copies of the test data from multiple memory cells, allowing comprehensive testing information to be captured and analyzed more efficiently. The compression circuitry generates a condensed representation of the test results that maintains all necessary testing information while reducing processing time.
3Quantity of substance
If data compression is implemented to reduce data communication connections, then fewer DQ connections are required, but data paths overhead increases
Solution Approach 1:
The invention extracts the data compression functionality into a separate, dedicated circuitry that operates independently during test mode. This extraction allows the compression logic to be optimized specifically for testing purposes without adding overhead to the normal data paths used during regular memory operations.
Solution Approach 2:
The data compression circuitry acts as an intermediary between the multiple memory cells and the data communication connections during testing. It mediates the data flow by compressing the information from multiple cells before transmission, thereby reducing the number of required DQ connections without permanently altering the normal data paths.
Data Source
AI summary
The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1≦j≦M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.