I/O Aware Processor Core Configuration via Boot Logic

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing information handling systems face inefficiencies in processor core utilization due to limitations in operating environments, where not all available processor cores can be effectively utilized, leading to suboptimal performance and resource management.

Innovation Solution

The system employs boot process logic to determine I/O device affinity and enable processor cores based on this information, allowing for selective core enablement on processor dies, thereby optimizing core usage and improving system performance by prioritizing cores proximate to I/O devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If all processor cores are enabled, then processing capacity is maximized, but operating performance is suboptimal due to inability to utilize all cores effectively

Engineering Contradiction:
Improveprocessing capacityVSAvoidoperating performance
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating between processor cores based on their I/O affinity characteristics. Instead of treating all cores uniformly, the system identifies and enables only those cores that are proximate to I/O devices, giving different functional properties to different cores based on their physical location and connectivity. This resolves the contradiction by enabling a subset of cores with optimal I/O access rather than all cores, thereby maintaining processing capacity while improving operating performance.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If processor cores distant from I/O devices are enabled, then total core count increases, but resource utilization efficiency decreases

Engineering Contradiction:
Improvecore countVSAvoidresource utilization efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent applies the extraction principle by selectively extracting and enabling only those processor cores that have direct I/O device affinity, while leaving other cores disabled. The boot process logic identifies cores proximate to I/O devices and enables only that specific subset. This resolves the contradiction by taking out the relevant subset of cores from the complete set, achieving optimal resource utilization efficiency while maintaining sufficient core count for the operating environment.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If I/O aware core selection is implemented, then operating performance improves, but system complexity increases

Engineering Contradiction:
Improveoperating performanceVSAvoidconfiguration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies self-service by implementing automatic detection and configuration of I/O-aware processor core enablement during the boot process. The system autonomously identifies which cores are proximate to I/O devices and configures them accordingly without requiring manual intervention or complex user setup. This resolves the contradiction by making the system self-configuring, thereby improving operating performance through intelligent core selection while minimizing the perceived complexity for the user.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10649943B2System and method for I/O aware processor configuration
Publication Date: 2020.05.12 DELL PROD LP
  • US10649943B2 patent drawing
  • US10649943B2 patent drawing
  • US10649943B2 patent drawing

AI summary

An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z−X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.