I/O Block Floorplanning for Die and BGA Package Cost Tradeoffs
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Solution Overview
Problem
Conventional physical design tools for integrated circuits (ICs) often optimize either die size or package cost but not both, leading to suboptimal total cost, and manual placement of interface blocks is labor-intensive.
Innovation Solution
A three-stage floorplanning process that systematically optimizes both die layout and package cost by generating candidate layouts and iteratively modifying them to minimize the sum of die and package costs, combined with a package design algorithm for Ball Grid Array (BGA) packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional physical design tools optimize die size, then die area is reduced, but package cost increases
Solution Approach 1:
The patent merges the optimization of die size and package cost into a single unified objective function. The floorplanning tool simultaneously considers both die area and package cost metrics, combining them into a total cost metric that is minimized through the optimization process. This allows the system to find layouts that balance both concerns rather than optimizing one at the expense of the other.
Solution Approach 2:
The system changes the optimization parameter from single-objective (either die size or package cost) to multi-objective optimization. By introducing a combined cost function that incorporates both die area and package cost parameters, the system can explore the trade-off space and identify optimal solutions that minimize total cost rather than individual components.
2Manufacturing precision
If interface blocks are manually placed, then placement precision is improved, but labor intensity increases
Solution Approach 1:
The floorplanning tool implements self-service automation where the system automatically performs interface block placement based on predefined constraints and optimization criteria. The tool evaluates multiple candidate layouts, estimates costs, and selects optimal placements without requiring manual intervention, thereby maintaining precision while eliminating labor-intensive manual placement operations.
Solution Approach 2:
The patent replaces the mechanical manual placement process with an automated computational system. The floorplanning tool uses algorithms to generate, evaluate, and select optimal interface block placements, substituting human manual operations with automated software-based mechanisms that achieve comparable or superior precision without the associated labor costs.
3Ease of manufacture
If multiple candidate layouts are generated, then design optimization is improved, but computation time increases
Solution Approach 1:
The system applies partial action by generating a limited but sufficient number of candidate layouts rather than exhaustively evaluating all possible configurations. The floorplanning tool creates multiple candidate layouts with different aspect ratios and I/O block arrangements, evaluates them using cost estimation, and selects the optimal ones, achieving good optimization results without the computational burden of complete enumeration.
Solution Approach 2:
The patent segments the floorplanning process into distinct stages: generating candidate layouts with different aspect ratios, placing I/O blocks along periphery edges, estimating costs for each configuration, and selecting optimal layouts. This segmentation allows the system to manage computational complexity by breaking down the overall optimization problem into smaller, more tractable sub-problems that can be solved efficiently.
Data Source
AI summary
A system for designing placement locations for Input/Output (I/O) blocks in an electronic device is disclosed. The system includes an interface and a processor. The interface is configured to receive a requirement that specifies at least multiple I/O blocks to be laid-out along a periphery of an electronic device that implements a network communication device. The processor is configured to generate a plurality of candidate layouts for the electronic device, the candidate layouts differing from one another at least in an arrangement of the specified I/O blocks along the periphery, to estimate respective costs associated with at least some of the candidate layouts, and to present at least some of the candidate layouts and the respective estimated costs to a user.