IO DC Blocking Circuit With Switchable ESD Path for Accurate Testing

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Solution Overview

Problem

Integrated circuits (ICs) face challenges with electrostatic discharge (ESD) susceptibility of series connected capacitors at input/output pins, which are also incompatible with DC testing, preventing accurate measurement due to voltage drops and inaccuracy in high-frequency testing.

Innovation Solution

Incorporating a dual-mode ESD protection circuit with a MOSFET connected in parallel to the DC blocking capacitor, allowing the ESD protection circuit to switch between operational and test modes, enabling ESD protection while allowing DC testing by short-circuiting the capacitor during test mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a DC blocking capacitor is connected to the IO pin to block DC voltage, then ESD protection is provided, but DC testing becomes impossible due to voltage drops and measurement inaccuracy

Engineering Contradiction:
ImproveESD protectionVSAvoidDC test measurement accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The ESD protection circuit is designed to dynamically change its state based on operational mode. A control signal switches the circuit between operational mode (where ESD protection is active and capacitor blocks DC) and test mode (where the protection circuit becomes conductive to short the capacitor, enabling accurate DC measurements). This dynamic reconfiguration resolves the contradiction by making the circuit properties adaptable to different operational requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the electrical parameters of the ESD protection circuit based on the operational mode. In operational mode, the circuit maintains high impedance to provide ESD protection while blocking DC. In test mode, the circuit transitions to low impedance state to short the capacitor, enabling DC current flow for accurate measurements. This parameter change allows the same circuit to satisfy both ESD protection and DC testing requirements.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If a DC blocking capacitor is used at the IO pin, then ESD susceptibility is reduced, but the circuit becomes incompatible with DC testing

Engineering Contradiction:
ImproveESD susceptibilityVSAvoidDC testing compatibility
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The ESD protection circuit is designed to perform multiple functions: in operational mode, it provides ESD protection while blocking DC voltage; in test mode, it becomes conductive to enable DC testing. This multi-functionality is achieved through a control signal that switches the circuit between two states, allowing the same circuit to adapt to different testing and operational requirements, thus resolving the contradiction between ESD protection and DC testing compatibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If high-frequency testing is used to achieve accurate measurements, then measurement accuracy improves, but testing cost increases significantly

Engineering Contradiction:
Improvemeasurement accuracyVSAvoidtesting cost
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The invention introduces a control signal as an intermediary mechanism that enables DC testing by temporarily modifying the circuit configuration. When the control signal activates test mode, it shorts the DC blocking capacitor, creating a conductive path that allows accurate DC measurements without requiring expensive high-frequency testing equipment. This intermediary control mechanism bridges the gap between simple DC testing capability and accurate measurement requirements, reducing testing costs while maintaining measurement precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides robust ESD protection during normal operation and enables accurate DC testing by short-circuiting the capacitor, reducing measurement errors and eliminating the need for costly high-frequency tests, thus improving IC testing efficiency.

Implementation Method 1

an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor

Methodology Applied
Scientific EffectField effect transistor conduction control:

Data Source

PatentEP4086642B1An integrated circuit
Publication Date: 2025.03.26 NXP BV
  • EP4086642B1 patent drawingFigure 1A~1B
  • EP4086642B1 patent drawingFigure 2
  • EP4086642B1 patent drawingFigure 3

AI summary

An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.