I/O Buffer Circuit Evaluation Using Variable Clock Delay Testing
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Solution Overview
Problem
Current integrated circuit testing methods, such as I/O loopback testing, become cost-prohibitive due to increasing complexity and number of interface nodes, especially as integrated circuit features shrink and operating frequencies rise, making it difficult to efficiently test future generations of memory devices with higher pin counts and faster clock rates.
Innovation Solution
The proposed solution involves performing rounds of loop-back tests on I/O buffer circuits with varying delays between transmit and receive clock signals, using automatic testing equipment with fine clock edge resolution to detect failures and determine if I/O buffer circuits satisfy test criteria, allowing for evaluation during wafer probe testing before assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive pre-assembly testing of every interface node is performed, then reliability of I/O buffer circuits is improved, but test cost and device complexity increase prohibitively
Solution Approach 1:
The patent segments the testing process into multiple test rounds, each targeting specific I/O buffer circuits with varying clock delays. Instead of testing all interface nodes simultaneously with complex equipment, the testing is divided into manageable segments that can be performed with simpler equipment, reducing overall device complexity while maintaining reliability coverage.
Solution Approach 2:
The patent performs preliminary testing actions by conducting multiple test rounds with different clock delays before final assembly. This preliminary action identifies potential failures early, allowing defective circuits to be detected and isolated before they require complex post-assembly testing, thereby reducing the complexity burden on final testing equipment.
2Productivity
If the number of I/O pins increases to support higher performance, then productivity and performance capability are improved, but test cost and measurement precision requirements increase
Solution Approach 1:
The patent employs dynamic testing by varying clock delays across multiple test rounds. The receive clock delay is adjusted dynamically to compensate for variations in I/O buffer circuit performance, allowing accurate measurement even with high pin counts and fast clock rates. This dynamic approach maintains measurement precision without requiring excessively high static resolution equipment.
Solution Approach 2:
The patent changes the delay parameter between transmit and receive clock signals across different test rounds. By varying this temporal parameter, the testing adapts to different circuit characteristics and performance levels, enabling precise measurement of high-speed interfaces without requiring proportionally higher measurement equipment specifications.
3Loss of time
If wafer probe testing is performed before assembly, then loss of time and waste are reduced, but equipment cost and complexity increase
Solution Approach 1:
The patent segments the wafer probe testing into multiple manageable test rounds that can be performed with relatively simple equipment. Each test round focuses on specific I/O buffer circuits with particular clock delay configurations, breaking down the complex task of testing all interface nodes into simpler, sequential segments that reduce equipment complexity requirements.
Solution Approach 2:
The patent enables wafer probe equipment to perform self-verification by using internal clock signals and delay mechanisms to conduct multiple test rounds. This self-service capability allows the equipment to perform comprehensive testing without requiring external complex testing apparatus, thereby reducing equipment complexity while maintaining the time-saving benefits of pre-assembly testing.
Data Source
AI summary
Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.