I/O Buffer Swing Reduction Circuit for BTI-Aware Gate Biasing
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Solution Overview
Problem
Bias Temperature Instability (BTI) effects cause performance degradation in metal-oxide-semiconductor field-effect-transistors (MOSFETs), particularly in input/output (I/O) buffer circuits due to voltage swings from supply voltages, leading to reliability issues and overdesign trade-offs in existing techniques.
Innovation Solution
A swing reduction circuit is introduced, comprising p-type and n-type configurations that adjust voltage swings at the gates of pMOSFETs and nMOSFETs in I/O buffer circuits, increasing the lower bound of voltage for p-type MOSFETs and decreasing the higher bound for n-type MOSFETs, thereby reducing the magnitude of voltage swings and minimizing BTI effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltages are reduced to save power and accommodate smaller MOSFET sizes, then power consumption decreases and device scaling is enabled, but Bias Temperature Instability (BTI) effects worsen causing threshold voltage changes and performance degradation
Solution Approach 1:
The patent applies preliminary action by adjusting the gate voltages of MOSFETs before they are subjected to supply voltage swings. Specifically, the gate voltages are pre-adjusted to compensate for expected threshold voltage shifts due to BTI effects, thereby maintaining stable operation despite reduced supply voltages and preventing performance degradation
2Productivity
If I/O buffer circuits operate with full supply voltage swings, then signal transmission capability is maintained, but BTI effects are exacerbated leading to reduced circuit lifetime
Solution Approach 1:
The patent applies local quality by selectively adjusting the gate voltages of specific MOSFETs within the I/O buffer circuit. Different gate voltages are applied to different MOSFETs depending on their position and function in the circuit, allowing the circuit to maintain full signal transmission capability while locally compensating for BTI effects to extend overall circuit lifetime
3Reliability
If overdesign techniques are used to compensate for BTI effects, then reliability is improved, but area and timing performance are degraded
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate voltage parameters of MOSFETs based on operating conditions and expected BTI effects. Instead of using fixed overdesign margins that increase area and timing complexity, the gate voltages are tuned to optimal values that provide reliability compensation without requiring additional circuit area or complex timing structures
Data Source
AI summary
A circuit includes: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, and a second swing reduction circuit coupled between the input/output pad and the buffer circuit. The first swing reduction circuit comprises a first transistor gated by a first bias voltage and comprises a second transistor drained by the first bias voltage. The first swing reduction circuit is configured to increase a voltage at a first node in the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage. The second swing reduction circuit is configured to reduce a voltage at a second node in the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.