I/O Buffer Jitter Modeling via Power Supply Noise Extraction
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Solution Overview
Problem
Traditional integrated circuit behavioral models fail to accurately capture timing characteristics, such as power-induced jitter effects, leading to inaccurate circuit analysis in high-speed designs.
Innovation Solution
The development of enhanced behavioral modeling techniques that include power-induced jitter effects by extracting and interpolating rising and falling waveform data from physical models under multiple input voltage conditions, using a three-layer software architecture with a simulation engine, behavioral modeling engine, and graphing module to generate accurate I/O buffer models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional behavioral models (IBIS) are used to describe electrical characteristics without proprietary information, then ease of manufacture and information protection are improved, but measurement precision and timing characteristic accuracy deteriorate
Solution Approach 1:
The patent creates behavioral model copies that replicate the timing characteristics and power-induced jitter effects of the original device without exposing proprietary internal structures. The behavioral model data files contain copied electrical characteristic information including rise/fall times, propagation delays, and jitter parameters that accurately represent the device's timing behavior while maintaining the non-disclosure of proprietary design details.
2Measurement precision
If traditional behavioral models are used for signal integrity analysis, then ease of operation is improved, but measurement precision of timing characteristics deteriorates due to inability to capture power-induced jitter effects
Solution Approach 1:
The patent enhances traditional behavioral models by adding specific parameters that characterize power-induced jitter effects. The behavioral model data files include parameters such as rise time, fall time, propagation delay, and jitter magnitude that are extracted from SPICE simulations under varying power supply conditions. These additional parameters enable accurate timing analysis while maintaining compatibility with existing signal integrity analysis tools and workflows.
3Measurement precision
If behavioral models extract only static electrical characteristics without dynamic timing data, then device complexity is reduced, but measurement precision of timing characteristics deteriorates
Solution Approach 1:
The patent performs preliminary SPICE simulations under multiple power supply conditions to extract rise/fall waveform data and calculate timing characteristics before generating the behavioral model. The simulation engine pre-computes propagation delays, rise/fall times, and jitter effects by analyzing voltage transitions at specified measurement points. This preliminary extraction of timing data from detailed simulations enables the behavioral model to accurately represent dynamic timing characteristics without requiring complex real-time calculations during signal integrity analysis.
Data Source
AI summary
Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method for behavioral modeling of jitters due to power supply noise for input/output (I/O) buffers. The method may include accessing physical model data describing a physical structure of an integrated circuit device, and accessing a behavioral model schema for evaluating electrical characteristics of the integrated circuit device including jitter effects introduced by power noise in the integrated circuit device. The method may further include generating behavioral model data based on the physical model data, the behavioral model data including the electrical characteristics of integrated circuit device. The method may further include providing a data file including the behavioral model data.