Input Output Buffer Circuit for Memory Systems
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Solution Overview
Problem
Current memory systems face challenges in reducing capacitance seen from nonvolatile memory devices during write and read operations, leading to faster operating speeds and increased data capacity but resulting in signal distortion.
Innovation Solution
The implementation of an input/output buffer circuit that connects a data channel to one of multiple internal data channels, utilizing a delay locked loop circuit for synchronization and a de-multiplexer to manage control signals, thereby reducing capacitance and minimizing signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory system increases operating speed and data capacity, then productivity is improved, but signal distortion increases due to higher capacitance
Solution Approach 1:
The patent divides the memory system into multiple independent data channels (first data channel and second data channel) that can operate simultaneously. By segmenting the data transmission paths, the capacitance load on each channel is reduced, allowing faster operating speeds without proportionally increasing signal distortion. Each channel handles a portion of the total data capacity, maintaining signal integrity while improving overall productivity.
2Productivity
If multiple data channels are used to increase data capacity, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple data channels (first data channel and second data channel) into a unified buffer circuit architecture. The input buffer and output buffer are merged structures that handle signals from multiple channels simultaneously, reducing the overall complexity compared to having separate buffer circuits for each channel. This merging approach maintains high data capacity while controlling device complexity through shared circuit resources.
Data Source
AI summary
Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.