I/O Buffer Calibration for Offset Transition Accuracy
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Solution Overview
Problem
Input or output buffer offsets in integrated circuit devices, such as NAND flash memory, lead to errors in setup and hold time requirements due to variabilities in fabrication and signal termination impedance, causing operational failures.
Innovation Solution
Applying specific voltage levels to the inputs of the I/O buffer until the logic level of the output transitions, using calibration logic and calibration circuitry to adjust the buffer offset by restricting or sourcing current, or adjusting resistances in the current paths regulated by the inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a differential amplifier is used in an I/O buffer, then the output voltage signal transitions when input voltage signals cross, but fabrication variabilities and impedance imbalances cause voltage offset that shifts the transition point
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before normal buffer operation. The calibration circuitry pre-adjusts the differential amplifier's offset by applying calibration voltages and measuring the transition point, then storing compensation values that are applied during subsequent operations to maintain accurate transition points despite fabrication variations
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the calibration voltage levels and resistance values in the calibration circuitry. By varying these parameters during calibration and operation, the system can compensate for offset variations and maintain precise transition points across different operating conditions and device variations
2Measurement precision
If calibration circuitry is added to mitigate buffer offset, then transition point accuracy improves, but device complexity increases
Solution Approach 1:
The patent merges the calibration circuitry with the existing I/O buffer structure, integrating offset calibration functionality into the differential amplifier framework. This combination allows the calibration circuits to share common elements with the main buffer, reducing overall complexity while maintaining transition point accuracy
Solution Approach 2:
The calibration circuitry is designed with multi-functionality, serving both as an offset calibration mechanism and as part of the normal signal path during operation. The same circuit elements are used for both calibration and signal processing, eliminating the need for completely separate calibration hardware and reducing device complexity
Data Source
AI summary
Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.