I/O Buffer Impedance Calibration for Drive and Split Termination
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Solution Overview
Problem
High-speed signal integrity issues arise in chip-to-chip interconnects due to transmission line effects like reflections, attenuation, and cross-talk, particularly in SDRAM memory systems, where existing solutions lack dynamic impedance control and often require external resistors, increasing costs and power consumption.
Innovation Solution
A combined drive and termination circuit with variable impedance pull-up and pull-down networks, dynamically configurable between drive and termination modes, using transistors in parallel to adjust impedance, and a calibration mechanism to set optimal transistor enablement for different operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed external resistors are used to match PCB trace impedance, then signal integrity is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the drive function and termination function into a single integrated circuit block. The termination resistors are integrated on-chip rather than being external discrete components, eliminating the need for separate external resistors while maintaining signal integrity through proper impedance matching of the PCB traces.
2Reliability
If I/O buffers have low output impedance for better noise immunity, then signal swing is improved, but signal reflections increase without proper termination
Solution Approach 1:
The patent implements dynamic impedance control where the output impedance of the I/O buffer can be adjusted based on operating conditions. The circuit includes control logic that dynamically selects between different impedance settings (e.g., low impedance for driving, high impedance for termination) to optimize both noise immunity and minimize reflections in different operational states.
Solution Approach 2:
The patent changes the impedance parameter of the I/O buffer dynamically. By using control signals to adjust the impedance value based on whether the buffer is in drive mode or termination mode, the circuit optimizes performance for different operational requirements while minimizing harmful reflections.
3Reliability
If separate drive and termination circuits are used, then signal integrity is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent merges the drive circuit and termination circuit into a single integrated structure. The same I/O buffer circuit performs both drive and termination functions by dynamically adjusting its impedance state, eliminating the need for separate dedicated termination circuits and reducing overall power consumption.
Solution Approach 2:
The I/O buffer circuit is designed to be multi-functional, serving both as a drive buffer and a termination circuit depending on the control signals applied. This universal circuit design reduces the total component count and power consumption compared to having separate dedicated circuits for each function.
Data Source
AI summary
A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.