IO Buffer Circuit Testing via Shared Test Bus and Pass Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for testing input and output buffer circuits in integrated circuits are limited by the need for direct connection to tester channels, restricting parallel testing and being costly, especially when dealing with various IO standards and voltage ranges.
Innovation Solution
Implementing a non-touch testing system using pass gates and test busses that allow selective coupling of IO circuit blocks to a tester device, enabling parallel testing of multiple ICs without requiring all IO pads to be connected, and utilizing thick gate transistors to support high voltage testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If direct connection to tester channels is used for testing input and output buffer circuits, then measurement accuracy is ensured, but the number of tester channels required increases and testing cost increases
Solution Approach 1:
The patent introduces an intermediary testing mechanism using pass gates and test busses that couple IO circuit blocks to tester channels indirectly. Instead of requiring direct connection between each IO pad and tester channel, the test bus acts as a shared intermediary that multiple IO circuit blocks can access through controllable pass gates, reducing the number of tester channels needed while maintaining measurement capability
Solution Approach 2:
The test bus is designed as a universal testing resource that can be shared by multiple IO circuit blocks. The pass gates enable a single tester channel to sequentially or parallel test multiple different IO buffers through the shared test bus, making the tester channel multi-functional and reducing overall hardware requirements
2Reliability
If all IO pads are connected to tester channels for comprehensive testing, then testing coverage is complete, but parallel testing capability is restricted and productivity decreases
Solution Approach 1:
The patent merges multiple testing paths into a shared test bus infrastructure. Multiple IO circuit blocks are combined and accessed through common test busses with pass gates, allowing the testing system to handle multiple devices or multiple buffers within a device simultaneously, thereby enabling parallel testing while maintaining comprehensive coverage
Solution Approach 2:
The pass gates provide dynamic control over the coupling between IO circuit blocks and the test bus. By dynamically enabling or disabling specific pass gates based on which buffers need testing, the system can flexibly configure testing paths to accommodate parallel testing of multiple ICs or multiple buffers, optimizing productivity without sacrificing coverage
3Adaptability or versatility
If extensive tester hardware is used to support various IO standards and voltage ranges, then testing versatility is achieved, but device complexity and cost increase
Solution Approach 1:
The patent employs parameter changes in the form of selectable voltage levels and test configurations through the pass gate control logic. The same test bus infrastructure can be dynamically reconfigured to test different IO standards by changing the voltage parameters and coupling configurations, allowing a single hardware platform to support multiple IO standards without requiring separate dedicated hardware for each standard
Data Source
AI summary
An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pass gate circuit. The first pass gate circuit and the second pass gate circuit are configurable to couple the second pad to the buffer circuit through the test bus during a test of the buffer circuit that is performed using the second pad.