I/O Buffer Voltage Testing via Boundary Scan Bypass Logic
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Solution Overview
Problem
The existing methods for testing semiconductor chip I/O pins using boundary scan infrastructure are time-consuming and lack precision, especially when performing voltage characterization tests, as they require shifting data through the boundary scan chain, which can be inefficient and prevent the use of high-precision test equipment like PPMU.
Innovation Solution
The proposed solution bypasses the shifting operation of the boundary scan chain by using combinational logic circuits to combine logic levels of I/O pins into test signals, allowing for concurrent testing and enabling the use of PPMU for more precise voltage characterization, thereby reducing testing time and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If boundary scan chain shifting is used for I/O pin testing, then testing can be performed using standard boundary scan infrastructure, but testing time is excessive and precision is limited
Solution Approach 1:
The patent segments the testing process by separating the voltage application function (performed by PPMU on selected I/O pins) from the data collection function (performed by boundary scan cells). This allows simultaneous voltage characterization and logic level detection without sequential shifting operations, resolving the contradiction between precision measurement and testing time.
Solution Approach 2:
The patent introduces boundary scan cells as intermediary components that capture logic levels directly from I/O pins during voltage characterization. These cells act as mediators between the PPMU measurement system and the test data output, enabling concurrent operation and eliminating the time-consuming shifting process while maintaining measurement precision.
2Measurement precision
If boundary scan chain shifting is used, then existing boundary scan infrastructure can be utilized, but high-precision test equipment like PPMU cannot be effectively used
Solution Approach 1:
The patent merges the capabilities of PPMU (for precise voltage measurement) with boundary scan cells (for logic level detection and data output) into a unified testing methodology. This combination allows high-precision equipment to be effectively used while maintaining compatibility with existing boundary scan infrastructure, resolving the contradiction between precision and complexity.
Solution Approach 2:
The patent makes the boundary scan infrastructure multi-functional by using boundary scan cells both for their traditional interconnect testing purpose and for capturing logic levels during voltage characterization. This universal usage eliminates the need for separate testing procedures, reducing complexity while enabling high-precision measurements.
3Productivity
If data is shifted through boundary scan chain, then test results can be output through TDO pin, but testing procedure becomes complex and time-consuming
Solution Approach 1:
The patent performs preliminary action by having boundary scan cells capture logic levels directly at the moment of voltage characterization, before any shifting operation is needed. This advance capture eliminates the subsequent time-consuming shifting process and simplifies the testing procedure, resolving the contradiction between productivity and ease of operation.
Data Source
AI summary
An integrated circuit device may include core circuitry, and a set of external interface buffer circuits coupled to the core circuitry. To improve test time and accuracy, as well as to simplify test procedures during voltage testing of the set of external interface buffer circuits, the integrated circuit device may include a test circuit and a combinational logic circuit coupled to the set of external interface buffer circuits. The combinational logic circuit is configured to combine a logic level of each of the external interface buffer circuits into a test signal, and the test circuit is configured to execute a voltage test on the set of external interface buffer circuits based on a logic level of the test signal.