High-Voltage I/O Buffer Without VCCAUX Power Sequencing
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Solution Overview
Problem
Integrated circuit (IC) devices using high voltage general purpose input/output (I/O) circuits face complexity due to the need for three separate voltages (VCCINT, VCCAUX, and VCCO), which complicates power sequencing and increases design and manufacturing costs.
Innovation Solution
A method and design for a high voltage I/O buffer that operates independently of the auxiliary power supply (VCCAUX) by using a VCCO detection circuit coupled to a bias generation circuit, level-shifter circuitry, and driver/pre-driver circuits, allowing direct conversion of core signals to the VCCO domain without relying on VCCAUX, thereby simplifying the power supply routing and reducing the number of power bumps and decoupling capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three separate voltages (VCCINT, VCCAUX, VCCO) are used in high voltage I/O circuits, then device protection and signal integrity are improved, but power supply complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the VCCAUX auxiliary power supply from the system by redesigning the I/O buffer to operate directly from VCCO. This removes the need for separate auxiliary voltage generation, routing, and decoupling infrastructure while maintaining device protection through alternative circuit design approaches.
Solution Approach 2:
The VCCO power supply is given multi-functionality to simultaneously serve both as the I/O buffer power supply and as the protection voltage source. The I/O buffer circuit is designed to perform both signal buffering and voltage protection functions using only the VCCO supply, eliminating the need for dedicated VCCAUX.
2Reliability
If three separate voltages are used, then I/O buffer performance is improved, but the number of power bumps and layout area increase
Solution Approach 1:
The patent merges the VCCAUX and VCCO power supply functions into a single VCCO supply. By combining these separate voltage domains into one unified power source, the physical footprint for power delivery infrastructure is reduced, eliminating redundant power bumps and decoupling capacitor locations.
Solution Approach 2:
The auxiliary power supply infrastructure (VCCAUX bumps, decoupling capacitors, routing) is extracted and removed from the design. The I/O buffer is redesigned to function without this extracted infrastructure, directly reducing layout area while maintaining performance through optimized circuit topology.
3Ease of operation
If VCCAUX is used for I/O buffer operation, then signal level translation is simplified, but power sequencing complexity increases
Solution Approach 1:
The VCCAUX intermediate voltage domain is extracted and removed from the power architecture. The I/O buffer is redesigned to perform level translation directly between core logic levels and I/O pin levels using only VCCO, eliminating the need for complex three-stage power sequencing (VCCINT, VCCAUX, VCCO).
Solution Approach 2:
The invention changes the voltage domain parameters by eliminating VCCAUX and having the I/O buffer operate directly in the VCCO domain. This parameter change simplifies the power sequencing requirements from three independent voltage ramps to a simpler two-voltage scheme, reducing sequencing complexity.
Data Source
AI summary
An input/output (I/O) buffer is implemented without an auxiliary power supply (VCCAUX). The input/output (I/O) buffer includes a connection to a VCCO power supply, a connection to a VCCINT power supply, a connection to a reference voltage, and a VCCO detection circuit coupled to a bias generation circuit. Further, the I/O buffer includes a transmitter circuit coupled to the bias generation circuit, and a receiver circuit coupled to an I/O pad.