I/O Bus Shared Memory System with Segmented Bus Lines
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Solution Overview
Problem
Existing memory systems with shared bus lines are limited in simultaneously accessing multiple memory chips due to the single bus structure, which restricts operations and increases system size and cost with discrete bus lines for high transfer rates.
Innovation Solution
A memory system configuration that combines discrete and shared bus lines, where discrete bus lines are used for point-to-point connections with the hub and shared bus lines for multiple memory devices, allowing the hub to execute logic for simultaneous operations across different subsets of bus lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared bus lines are used to connect multiple memory chips to the hub, then the system size and cost are reduced, but the hub cannot address different operations to different memory chips simultaneously
Solution Approach 1:
The bus lines are segmented into shared bus lines and discrete bus lines. Shared bus lines connect the hub to multiple memory chips for common control signals, while discrete bus lines provide dedicated data paths for simultaneous independent operations on different memory chips.
Solution Approach 2:
The shared bus lines serve multiple memory chips simultaneously for control and address signals, while discrete bus lines enable independent data transfers. This multi-functional bus structure allows the hub to perform simultaneous operations on different memory chips.
2Productivity
If discrete bus lines are used to connect each memory chip to the hub, then simultaneous access to multiple memory chips is enabled, but the system size and cost increase due to increasing pin counts and bus line counts
Solution Approach 1:
The bus structure is segmented into shared control lines and discrete data lines. This segmentation allows simultaneous access to multiple memory chips while reducing the total number of pin counts compared to fully discrete connections.
Solution Approach 2:
Shared bus lines are merged for control and address signals that are common to multiple memory chips, while discrete bus lines are used only for data transfers. This combining approach reduces redundancy and optimizes the system size.
3Device complexity
If shared bus lines are used, then the number of bus lines is reduced, but the transfer rate is limited due to the single bus structure
Solution Approach 1:
The bus system is segmented into shared control bus lines and discrete data bus lines. This segmentation enables parallel data transfers on discrete lines while maintaining a reduced control bus structure, thereby increasing overall transfer rates.
Solution Approach 2:
The discrete bus lines enable continuous simultaneous data transfers to multiple memory chips without the bottlenecks of shared bus arbitration, maintaining high transfer rates while the shared bus lines continuously manage control signals.
Data Source
AI summary
A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.