I/O Cache Partitioning for Scalable Virtualization

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Solution Overview

Problem

Current I/O virtualization technologies, such as SR-IOV, face challenges in scalability and performance when sharing I/O devices across isolated domains, and they struggle to incorporate advanced features like address translation and live migration without hardware upgrades.

Innovation Solution

The implementation of Scalable I/O Virtualization (SIOV) architecture, which enables flexible composition of virtual devices for device sharing, uses software-defined capabilities to provide advanced features like address translation and live migration, and maps SR-IOV virtual functions to SIOV ADIs to enhance existing devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SR-IOV is used for I/O virtualization, then hardware-assisted high performance I/O virtualization is achieved, but scalability and performance deteriorate when sharing I/O devices across isolated domains

Engineering Contradiction:
ImproveI/O virtualization performanceVSAvoidscalability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the I/O device sharing architecture into multiple isolated domains, each with its own I/O virtualization instance. This segmentation allows each domain to operate independently with guaranteed performance while enabling overall system scalability through controlled sharing mechanisms between domains.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary I/O virtualization layer that mediates between physical I/O devices and multiple isolated domains. This intermediary manages resource allocation, address translation, and live migration operations, resolving the contradiction by providing both hardware-assisted performance and software-controlled scalability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If hardware-assisted I/O virtualization is implemented, then high performance is achieved, but advanced features like address translation and live migration cannot be incorporated without hardware upgrades

Engineering Contradiction:
ImproveI/O operation speedVSAvoidfeature integration capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal I/O virtualization platform that combines hardware-assisted virtualization capabilities with software-defined feature extensions. This multi-functional approach allows the system to deliver hardware-level performance while simultaneously supporting advanced features like address translation and live migration through software layers.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the I/O virtualization system by introducing software-controlled address translation and migration parameters on top of hardware-assisted virtualization. This allows dynamic adjustment of features without requiring hardware modifications, maintaining high performance while enabling feature flexibility.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If a single shared I/O cache is used, then resource utilization is improved, but cache performance deteriorates due to conflicts from multiple I/O devices

Engineering Contradiction:
Improvecache resource utilizationVSAvoidcache access speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent segments the shared I/O cache into multiple isolated partitions, each dedicated to specific I/O devices or domains. This segmentation reduces cache conflicts by separating access patterns while maintaining overall high utilization through efficient partition management and dynamic allocation mechanisms.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250147886A1I/O cache partitioning
Publication Date: 2025.05.08 INTEL CORP
  • US20250147886A1 patent drawing
  • US20250147886A1 patent drawing
  • US20250147886A1 patent drawing

AI summary

A computing device includes last level cache (LLC) for processing cores and a separate input/output (I/O) LLC for use in facilitating data transfers between the computing device and one or more I/O devices. The I/O LLC is configured to include a set of partitions corresponding to a set of classes. Usage of the partitions in the set of partitions is monitored and the set of partitions is dynamically adjusted based on the usage. A process in a particular one of the classes makes a data request and a particular one of the partitions associated with the particular class is used in the data request.