I/O Cell Wire Connector for High Current Circuit Reliability
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Solution Overview
Problem
In modern integrated circuits, high current circuitry often experiences current crowding issues due to inadequate sizing and positioning of connection buses, leading to potential failures in electrostatic discharge (ESD) protection and other high current components, especially in wide I/O cells where manual placement becomes time-intensive and error-prone.
Innovation Solution
The solution involves sizing and positioning the connection bus to match the high current circuitry area, ensuring that through vias are aligned for efficient current flow, reducing lateral current travel and crowding by customizing the I/O pin size based on the location of ESD protection devices or other high current components, and using a bump or bond pad for connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the connection bus is sized to match the high current circuitry area, then current crowding is reduced and reliability is improved, but the device complexity increases due to customized sizing and positioning requirements
Solution Approach 1:
The connection bus is customized with specific sizing and positioning that matches the local requirements of high current circuitry areas. Rather than using a uniform connection bus design throughout the device, the patent applies locally-optimized connection bus dimensions and positions specifically where high current circuitry is located, thereby reducing current crowding at critical locations without unnecessarily complicating the entire device structure.
Solution Approach 2:
The patent performs preliminary identification and sizing of connection buses based on the known locations and areas of high current circuitry before final device assembly. By pre-determining the appropriate connection bus dimensions and positions based on the high current circuitry layout, the design process is streamlined and avoids complex adjustments during later stages, thereby reducing overall device complexity while maintaining reliability.
2Manufacturing precision
If manual placement of connection buses is used in wide I/O cells, then positioning accuracy can be achieved, but the manufacturing time increases and errors become more frequent
Solution Approach 1:
The patent transforms the connection bus design from manual placement parameters to standardized dimensional parameters that are directly derived from the high current circuitry area. By changing the design approach from manual coordinate specification to area-based dimensional calculation, the positioning accuracy is maintained while enabling automated manufacturing processes that significantly improve productivity and reduce errors in wide I/O cell production.
3Ease of manufacture
If the connection bus is positioned away from the high current circuitry, then manufacturing is simpler, but current crowding increases and reliability decreases
Solution Approach 1:
The patent segments the connection bus design into distinct standardized dimensions (width, length, position) that are independently optimized for their specific functions. This segmentation allows the connection bus to be positioned close to high current circuitry for optimal current flow while maintaining standardized manufacturing processes for each dimensional parameter, thereby achieving both ease of manufacture and high reliability without requiring complex integrated solutions.
Data Source
AI summary
An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.