I/O Circuit Gate Control for High-Voltage Input Power Reduction
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Solution Overview
Problem
Conventional input/output circuits face challenges in reducing power consumption and increasing operation frequency, especially when handling high voltage inputs, as they often result in unnecessary current paths and increased power consumption due to slow transistor response times and PN junction diode formation.
Innovation Solution
The input/output circuit design includes a pull-up and pull-down output transistor system with complementary logic circuits and a gate signal generation unit, which activates or inactivates transistors based on the enable signal and data, preventing current paths to the power supply or ground even with high voltage inputs, and utilizes a back gate control circuit to manage transistor states effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a tolerant input/output circuit is used to handle high voltage inputs, then the circuit can operate without difficulty even when input signal voltage exceeds power supply voltage, but unnecessary current paths are formed and power consumption increases
Solution Approach 1:
The back gate control circuit proactively supplies voltage to the N-well before high voltage inputs are applied, preventing the formation of PN junction diodes and subsequent current paths. This preliminary action eliminates the need for corrective measures after current paths are formed, directly reducing power consumption while maintaining high voltage tolerance.
Solution Approach 2:
The N-well acts as an intermediary element between the power supply voltage and the high voltage input signal. By controlling the voltage level of the N-well through the back gate control circuit, the patent prevents direct interaction between high voltage inputs and the power supply, thereby blocking unnecessary current paths while maintaining circuit functionality.
2Loss of energy
If the supply of power supply voltage is suspended during standby state to reduce power consumption, then power consumption is reduced, but the circuit cannot quickly respond when high voltage inputs are applied
Solution Approach 1:
The back gate control circuit maintains voltage supply to the N-well during standby state, preparing the circuit in advance for high voltage input conditions. This preliminary voltage supply ensures that when high voltage inputs are applied, the circuit can immediately respond without delay, while still maintaining low power consumption by only supplying voltage to the N-well rather than the entire circuit.
3Productivity
If transistors are designed for fast switching to increase operation frequency, then operation frequency is improved, but unnecessary current paths are more likely to form with high voltage inputs
Solution Approach 1:
The controlled N-well voltage acts as an intermediary that allows fast switching transistors to operate at high frequencies while preventing harmful interactions with high voltage inputs. The N-well voltage control creates an electrical barrier that blocks current paths from forming, even when transistors switch rapidly, thus maintaining both high operation frequency and low power consumption.
Data Source
AI summary
An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor; a pull-down output transistor including a gate; a second logic circuit coupled to the gate of the pull-down output transistor, and the second logic circuit inactivating the pull-down output transistor in the input mode; and a gate signal generation unit configured to generate a gate signal for inactivating the pull-up output transistor in accordance with the enable signal and an input signal provided from an external device to the input/output terminal in the input mode.