I/O Circuit Compensation for NBTI-Induced Pulse Width Drift
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Solution Overview
Problem
Semiconductor devices experience performance and reliability degradation due to negative bias temperature instability (NBTI) affecting PMOS transistors, leading to timing errors and pulse width changes in output signals.
Innovation Solution
An input/output (I/O) circuit configuration that applies stress to transmission paths during a test mode and buffers signals using changed drivability, generating first and second transmission signals in normal mode to prevent pulse width changes, utilizing input control and output control circuits with signal synthesis and transmission circuits to drive output signals through non-degraded transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If PMOS transistors are used in transmission paths, then device complexity is reduced, but pulse width changes and timing errors occur due to NBTI degradation
Solution Approach 1:
The transmission path is segmented into multiple parallel paths (first transmission path with PMOS transistors, second transmission path with NMOS transistors). Each path handles different signal components, allowing the circuit to exploit the advantages of each transistor type while compensating for their individual weaknesses through signal combination
Solution Approach 2:
The circuit changes the operational parameters of transistors by applying stress during test mode to intentionally induce NBTI effects, then using these changed parameters to generate compensation signals that offset timing errors during normal operation
2Reliability
If stress is applied to transmission paths during test mode, then timing error compensation can be achieved, but device complexity and test procedure complexity increase
Solution Approach 1:
The same transmission paths and transistors serve dual functions: they transmit data signals during normal mode and generate compensation signals during test mode. The input control circuit and output control circuit manage these mode transitions, allowing one hardware structure to perform multiple functions without requiring separate dedicated circuits
Solution Approach 2:
The circuit performs preliminary characterization of transistor degradation by applying stress during test mode before normal operation. This preliminary action allows the system to pre-determine compensation parameters that will be used during subsequent normal operation, ensuring timing accuracy without real-time complex control
3Reliability
If NBTI phenomenon is allowed to occur, then transistor drivability changes provide compensation capability, but performance degradation occurs during normal operation
Solution Approach 1:
The circuit operates in periodic cycles between test mode and normal mode. During test mode, stress is applied to induce NBTI and characterize degradation. During normal mode, the characterized degradation parameters are used to generate compensation signals. This periodic switching allows the system to harvest the compensation benefit of NBTI while minimizing its harmful effects on productivity
Data Source
AI summary
An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.