I/O Circuit Segmentation for Concurrent Memory Access
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Solution Overview
Problem
In semiconductor devices, the global input/output line is often occupied during row copy operations, preventing access to memory cells, which limits the ability to perform normal input/output operations and row copy operations between banks.
Innovation Solution
The input/output circuit includes multiple memory cell units and selection units that selectively connect to global input/output lines, allowing independent output operations and enabling access to memory cells through alternative paths, even when one global line is occupied, by using a selection circuit to control path connections based on path control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single global input/output line is used for both normal input/output operations and row copy operations, then the device complexity is reduced, but the reliability of memory cell access deteriorates when the line is occupied
Solution Approach 1:
The invention divides the single global input/output line into multiple separate global input/output lines (first global input/output line and second global input/output line). This segmentation allows different memory cell units to have dedicated access paths, ensuring that when one line is occupied by a row copy operation, other lines remain available for normal input/output operations, thus maintaining memory cell access reliability without excessive complexity
Solution Approach 2:
Each memory cell unit is designed with dual functionality to access either the first or second global input/output line based on operation mode. The selection circuit enables each memory cell unit to be universally connected to either line, allowing the system to flexibly allocate resources and maintain reliability under different operational conditions
2Reliability
If multiple global input/output lines are provided for each memory cell unit, then the accessibility of memory cells is improved, but the device complexity increases
Solution Approach 1:
The invention segments the memory cell units into different groups (first memory cell unit and second memory cell unit), where each group is assigned to a specific global input/output line. This segmentation provides dedicated access paths that improve reliability while avoiding the need for every memory cell unit to have multiple independent connection paths, thus controlling circuit complexity
Solution Approach 2:
The selection circuit acts as an intermediary that manages the connection between memory cell units and global input/output lines. It receives path control signals and dynamically routes connections, providing intelligent resource allocation that improves accessibility without requiring hardwired multiple paths for each memory cell unit, thereby controlling overall circuit complexity
3Adaptability or versatility
If the global input/output line is occupied by a row copy operation, then the row copy function is enabled, but the normal input/output operations are blocked
Solution Approach 1:
The invention segments the input/output operations into separate channels by providing multiple global input/output lines. When a row copy operation occupies the first global input/output line, normal input/output operations can simultaneously proceed through the second global input/output line, and vice versa. This segmentation enables concurrent operations and maintains overall system productivity while preserving operational flexibility
Solution Approach 2:
The invention merges multiple global input/output lines into a unified system managed by a single selection circuit and path control logic. This merging allows the system to coordinate multiple operation types (normal input/output and row copy) across different lines, enabling simultaneous execution and maintaining both operational flexibility and throughput
Data Source
AI summary
An input/output circuit according to an embodiment includes a plurality of memory cell units configured to independently perform output operations, each of the memory cell units including an input/output line, a selection circuit including a plurality of selection units, each selection unit setting a path to a global input/output line connected to each of the selection units, the number of the selection units being the same as the number of the memory cell units, the selection circuit selecting one of the plurality of memory cell units based on a path control signal and electrically connecting the input/output line of the selected memory cell unit to the global input/output lines of the plurality of selection units, and a plurality of input/output pad groups coupled to the global input/output lines.