Input Output Circuit Speed Adaptation for Semiconductor Testing
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Solution Overview
Problem
High-speed semiconductor apparatuses cannot be effectively tested using contemporary low-speed test equipment due to limitations in providing high-speed external clocks, data transfer rates, and data strobe signal handling, leading to increased costs and reduced productivity.
Innovation Solution
A system with an input/output circuit that operates in both normal and test modes, allowing high-speed semiconductor apparatuses to be tested on both high-speed and low-speed test equipment by controlling signal speeds and generating appropriate data groups and strobe signals through pulse generation, latch units, and multiplexer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-speed semiconductor apparatus is tested on low-speed test equipment, then manufacturing cost is reduced and productivity increases, but the test equipment cannot provide high-speed external clocks and data transfer rates required for high-speed operations
Solution Approach 1:
The patent changes the speed parameter of the external clock by using a division circuit that divides the high-speed internal clock signal to generate a low-speed external clock signal. This allows the semiconductor apparatus to operate at high speed internally while interfacing with low-speed test equipment, resolving the contradiction between high-speed operation and low-speed testing capability
Solution Approach 2:
The patent introduces an intermediary clock division circuit that acts as a bridge between the high-speed internal clock and the low-speed external clock. This intermediary component enables the high-speed semiconductor apparatus to be tested on low-speed equipment by translating between different speed domains
2Ease of manufacture
If a high-speed semiconductor apparatus is tested on low-speed test equipment, then manufacturing cost is reduced, but the test equipment cannot provide high-speed data transfer rates
Solution Approach 1:
The patent changes the data transfer rate parameter by using a division circuit that divides the high-speed internal clock to generate a low-speed external clock. This clock division enables data to be transferred at high speed internally while being transferred at low speed externally to the test equipment, reducing manufacturing costs without sacrificing internal performance
Solution Approach 2:
The patent segments the data transfer process into two distinct stages: high-speed internal data transfer within the semiconductor apparatus, and low-speed external data transfer to the test equipment. This segmentation allows each stage to operate at appropriate speeds, reducing overall system cost while maintaining high-speed capability where needed
3Productivity
If a high-speed semiconductor apparatus is tested on low-speed test equipment, then productivity increases, but the test equipment cannot normally receive high-speed data output
Solution Approach 1:
The patent changes the speed parameter of the output data by using a division circuit that divides the high-speed internal clock to generate a low-speed external clock. This ensures that data output speed matches the reception capability of the low-speed test equipment, eliminating data loss and ensuring accurate measurement while maintaining high productivity
Solution Approach 2:
The patent introduces an intermediary clock division mechanism that mediates between the high-speed data output of the semiconductor apparatus and the low-speed data reception capability of the test equipment. This intermediary ensures proper timing and speed matching, preventing data loss and ensuring accurate reception
4Reliability
If high-speed test equipment is invested in to test high-speed semiconductor apparatus, then testing capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the clock speed parameter through division, enabling the same semiconductor apparatus to be tested on both low-speed and high-speed equipment. This parameter transformation allows existing low-speed test equipment to effectively test high-speed apparatus, eliminating the need for expensive high-speed test equipment investments while maintaining full testing capability
Solution Approach 2:
The patent makes the semiconductor apparatus universally testable by both low-speed and high-speed test equipment through the clock division circuit. This multi-functionality allows a single apparatus design to be tested on existing low-speed equipment or future high-speed equipment, providing flexibility and eliminating the need for specialized expensive test equipment
Data Source
AI summary
A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus.