I/O Completion Polling for Low Latency Storage

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Solution Overview

Problem

Conventional I/O processing protocols result in excessive processing overhead when used with low-latency storage devices, particularly in virtualized environments, leading to unacceptable latency and throughput issues.

Innovation Solution

Implementing a Deferred Procedure Call (DPC) that polls for I/O completion, scheduled to run at the PASSIVE IRQL level, allowing for efficient CPU usage and balanced throughput without dedicated threads, and utilizing Simultaneous Multi-Threading processors to manage I/O requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional interrupt-based I/O processing is used, then the system can handle I/O requests through standard protocols, but the processing overhead becomes excessive and latency increases

Engineering Contradiction:
ImproveI/O processing reliabilityVSAvoidI/O latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the interrupt handling mechanism from the I/O completion process and replaces it with a polling mechanism. The storage device no longer generates interrupts for I/O completion; instead, the host system actively polls the device to check completion status, removing the interrupt overhead entirely.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host system preliminarily establishes a polling mechanism in advance, where the host CPU periodically checks the storage device's completion queue or status registers. This preliminary setup eliminates the need for reactive interrupt handling, reducing latency by having the host proactively check for completion rather than waiting for an interrupt.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If interrupt-based processing is used in virtualized environments, then standard I/O handling is maintained, but the interrupt must traverse multiple layers (physical CPU, hypervisor, virtual CPU) increasing processing overhead

Engineering Contradiction:
ImproveVirtualization compatibilityVSAvoidI/O throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent removes the interrupt mechanism from the virtualized I/O path. By using polling instead, the I/O completion notification does not need to traverse the hypervisor layer or context-switch between physical and virtual CPUs, eliminating the overhead associated with virtualized interrupt handling.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a completion queue or status register as an intermediary structure between the storage device and the host. The host polls this intermediary to determine I/O completion, bypassing the need for direct interrupt communication through the virtualization layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If storage device delivers I/O interrupts to multiple CPUs, then load distribution is achieved, but CPU saturation occurs before maximum throughput is reached

Engineering Contradiction:
ImproveI/O throughputVSAvoidCPU management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent inverts the traditional interrupt delivery model. Instead of the storage device actively delivering interrupts to CPUs, the host CPU passively polls the storage device for completion status. This inversion gives the host full control over polling frequency and CPU selection, preventing CPU saturation.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The polling mechanism is dynamic, allowing the host system to adjust polling frequency, select which CPUs perform polling, and modify queue depths based on system conditions. This dynamic control prevents any single CPU from becoming saturated while maintaining high throughput.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3853724B1I/O completion polling for low latency storage device
Publication Date: 2023.06.14 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3853724B1 patent drawingFigure 1
  • EP3853724B1 patent drawingFigure 2
  • EP3853724B1 patent drawingFigure 3

AI summary

An I/O processing system includes reception of a request to perform an I/O operation from a user-mode application, providing of the request to a storage device, scheduling of an operating system deferred procedure call to determine whether the storage device has completed the I/O operation, execution of the scheduled deferred procedure call to determine that the storage device has completed the I/O operation, and transmission of a return corresponding to the completed I/O operation to the user-mode application.