Input Output Control Device for Memory Verification Frequency Synchronization
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Solution Overview
Problem
The verification of electronic circuits with high memory requirements is challenging due to the mismatch in operating frequencies between FPGA verification circuits and DRAM or SRAM memory devices, leading to inaccurate performance verification and increased costs with SRAM.
Innovation Solution
An input output control device is introduced, connected between the verification circuit and the semiconductor memory device, which includes a first port for receiving and outputting read transactions and responses, and a buffer device that delays outputs to synchronize frequencies, using a band counter and elapse cycle counters to manage data access and responses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM is used for verification due to its high operating frequency, then verification speed is improved, but verification accuracy deteriorates because the frequency mismatch causes performance verification to be inaccurate
Solution Approach 1:
An input output control device is introduced as an intermediary component between the verification circuit and the semiconductor memory device. This control device includes a buffer device that delays the output of read transactions and read responses, acting as a mediator to synchronize the frequency mismatch between the high-speed DRAM and the FPGA verification circuit, thereby maintaining both verification speed and accuracy
2Measurement precision
If SRAM is used instead of DRAM to match the verification circuit frequency, then verification accuracy is improved, but verification cost increases
Solution Approach 1:
The input output control device serves as a cost-effective intermediary solution that allows the continued use of inexpensive DRAM while achieving accurate verification. Rather than replacing DRAM with expensive SRAM, the control device with its buffer mechanism provides the necessary frequency synchronization at lower cost
Solution Approach 2:
The buffer device dynamically adjusts the timing parameters of read transactions and read responses by introducing controllable delays. This parameter adjustment allows the system to accommodate frequency differences between DRAM and FPGA, achieving accurate verification without changing the memory device type or incurring additional costs
Data Source
AI summary
An input output control device between a verification circuit and a semiconductor memory device includes: a first port that receives a read transaction for requesting reading of data in the semiconductor memory device from the verification circuit, and outputs a read response to the verification circuit; a second port that outputs the read transaction to the semiconductor memory device, and receives the read response output from the semiconductor memory device in response to the read transaction; and a buffer device that delays at least one of an output of the read transaction to the semiconductor memory device and an output of the read response to the verification circuit.