I/O Controller RDMA Message Write via Doorbell Signal

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Solution Overview

Problem

The latency in data transfer from a server to a client in conventional computing systems using RDMA protocols is high due to the number of main memory read operations performed by the server's I/O controller, despite efforts to reduce latency by placing data near the descriptor in the server's main system memory.

Innovation Solution

Writing messages directly from system memory to the I/O controller's memory space, including both data and descriptors, without involving host system memory reads, and using doorbell signals to manage resources dynamically, allowing the I/O controller to execute RDMA operations independently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is placed in line with descriptor in server's main system memory, then data transfer latency is reduced, but latency remains greater than desirable

Engineering Contradiction:
Improvedata transfer latencyVSAvoiddata transfer efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent extracts the data and descriptor from the host system memory and places them directly into the I/O controller's local memory space. This eliminates the need for the I/O controller to read from host memory, thereby removing the latency bottleneck and achieving near-instantaneous data transfer.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a doorbell mechanism as an intermediary signal to notify the I/O controller when data is ready in the local memory space. This mediator enables efficient communication between the host and I/O controller without requiring continuous memory reads, reducing latency while maintaining productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If I/O controller reads data from host main memory, then data can be transferred to client, but multiple memory read operations increase latency

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidmemory read operation latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by having the host write both the data and descriptor directly into the I/O controller's local memory space before the I/O controller needs to process the data. This pre-positioning of data eliminates subsequent memory read operations and reduces latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The I/O controller serves itself by reading data from its own local memory space rather than from the host memory. This self-service capability eliminates the dependency on host memory read operations, reducing latency while maintaining data transfer productivity.

Inventive Principle:
Principle #25Self-service

3Loss of time

If host system memory reads are eliminated, then latency is reduced, but resource management complexity increases

Engineering Contradiction:
Improvedata transfer latencyVSAvoidresource management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses a doorbell mechanism as feedback to notify the I/O controller when data is ready in the local memory space. This feedback mechanism simplifies resource management by providing clear, direct signals without requiring complex coordination protocols.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent implements dynamic resource management by allowing the I/O controller to independently manage its local memory space and doorbell signals without host intervention. This dynamic approach reduces latency while keeping resource management complexity manageable through straightforward signaling protocols.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9405725B2Writing message to controller memory space
Publication Date: 2016.08.02 INTEL CORP
  • US9405725B2 patent drawing
  • US9405725B2 patent drawing
  • US9405725B2 patent drawing

AI summary

An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred.