Semiconductor I/O Controller Segmentation for High-Speed Testing
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Solution Overview
Problem
Current semiconductor packaging techniques, such as system-in-package (SiP) and chip-on-chip (CoC), face challenges in efficiently testing and verifying the functionality of buffers and drivers through micro-bump pads, particularly in high-frequency operations where data transmission speeds and signal integrity are critical.
Innovation Solution
A semiconductor system with dual I/O units and a controller that employs mode set signals, chip selection signals, and external clock signals to enable multiple operational modes, allowing for signal transmission and reception through various paths, thereby facilitating the execution of normal, test, first, and second modes to verify interface normality/abnormality and optimize data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip-on-chip (CoC) technique is used to increase memory capacity in a single package, then memory capacity is improved, but testing and verification of buffers and drivers through micro-bump pads becomes difficult
Solution Approach 1:
The patent segments the I/O controllers into multiple independent units (first I/O controller and second I/O controller), each capable of independent operation and testing. This segmentation allows test operations to be performed on individual I/O controllers through specific pads, resolving the difficulty of testing in CoC packages by enabling isolated verification of each segment rather than requiring testing of the entire integrated system at once.
Solution Approach 2:
The patent introduces an intermediary testing mechanism where the first I/O controller can receive test signals through the first pad and the second I/O controller can receive test signals through the second pad. This intermediary signal path allows external testing equipment to verify buffer and driver functionality through dedicated test paths, solving the measurement difficulty without requiring physical access to internal micro-bump pad connections.
2Speed
If micro-bump pads are used to improve data transmission speeds, then data transmission speed is improved, but signal integrity verification becomes more challenging
Solution Approach 1:
The patent implements preliminary testing actions by enabling test operations before final package assembly. The first and second I/O controllers can be independently tested through their respective pads while still accessible, allowing verification of signal integrity and buffer/driver functionality before the micro-bump pads are permanently connected. This preliminary verification ensures signal integrity is maintained in the high-speed micro-bump pad connections.
Solution Approach 2:
The patent establishes feedback mechanisms where test signals can be input through the first or second pads and the responses can be observed to verify buffer and driver functionality. This feedback loop allows continuous verification of signal integrity during testing, ensuring that the high-speed micro-bump pad connections maintain reliable signal transmission even at increased data rates.
3Adaptability or versatility
If multiple I/O controllers are integrated in a single package, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent implements universality by designing the first and second I/O controllers with identical functional capabilities, where either controller can operate in any mode (normal mode or test mode) and either pad (first pad or second pad) can serve as input or output. This multi-functionality reduces device complexity by using standardized, interchangeable components rather than requiring specialized designs for each I/O controller, thereby maintaining high functionality while controlling complexity through design uniformity.
Data Source
AI summary
A semiconductor device may include a first input/output (I/O) unit and a second I/O unit. The first I/O unit may include a first input path that receives a signal through a first pad and a first output path and a first I/O controller that output a signal to the first pad. The second I/O unit may include a second input path that receives a signal through a second pad and a second output path and a second I/O controller that output a signal to the second pad.