IO DC Blocking Circuit With Switchable ESD Test Bypass
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits (ICs) with series connected capacitors at input/output (IO) pins face challenges with electrostatic discharge (ESD) susceptibility and the inability to perform DC testing due to the blocking nature of these capacitors.
Innovation Solution
The integration of a dual mode ESD protection circuit within each DC blocking module, which includes a capacitor and an ESD protection circuit connected in parallel. This ESD protection circuit has a control terminal that receives a control signal to switch between an operational mode for ESD protection and a test mode that short-circuits the capacitor, enabling DC testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is connected in series at an IO pin to block DC voltage, then ESD protection is provided, but DC testing becomes impossible
Solution Approach 1:
The ESD protection circuit is designed to dynamically change its state based on operational mode. During normal operation, the circuit maintains high impedance to provide ESD protection. During DC testing, a control signal activates the circuit to switch to low impedance state, enabling DC current flow through the capacitor while maintaining ESD protection functionality when inactive
Solution Approach 2:
The ESD protection circuit changes its electrical parameters (impedance state) based on control signals. The circuit transitions between high impedance state (providing ESD protection) and low impedance state (enabling DC testing), allowing the same circuit to serve dual purposes under different operational conditions
2Object-affected harmful factors
If an ESD protection circuit is added in parallel to the capacitor, then ESD susceptibility is reduced, but the circuit complexity increases
Solution Approach 1:
The ESD protection circuit is designed to perform multiple functions: providing ESD protection during normal operation and enabling DC testing during test mode. This multi-functionality reduces the need for separate dedicated circuits, thereby minimizing the increase in overall circuit complexity while addressing both ESD susceptibility and DC testing requirements
Solution Approach 2:
The ESD protection functionality and DC test enablement functionality are merged into a single integrated circuit block. By combining these functions into one circuit with dual operating modes, the patent avoids the complexity of having separate ESD protection circuits and separate DC test circuits, achieving both goals with minimal additional complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual mode ESD protection circuit effectively provides ESD protection in operational mode while allowing for DC test measurements in test mode, overcoming the limitations of ESD susceptibility and the inability to perform DC testing.
Implementation Method 1
a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC
Implementation Method 2
an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor
Data Source
AI summary
An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.