I/O Destaging Bandwidth Control via Dynamic Throttle

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Solution Overview

Problem

Storage arrays face performance issues due to write pending states when the rate of write I/O operations exceeds the destaging capacity, leading to increased write times and unpredictable throughput, as the destaging process competes with foreground processing for processor bandwidth.

Innovation Solution

Implementing a throttle controller to vary the destage frequency based on usage thresholds (usagemin and usagemax) and a throttling factor, which adjusts the destage frequency inversely proportional to the throttling factor, allowing for more efficient matching of destaging activity to user I/O rates, thereby stabilizing I/O throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If destaging runs at high frequency to clear cache space, then cache availability is improved, but foreground I/O throughput deteriorates due to processor bandwidth competition

Engineering Contradiction:
Improvecache availabilityVSAvoidforeground I/O throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The destage frequency is made dynamic rather than fixed. The throttle controller continuously monitors cache usage and adjusts destage frequency in real-time based on current system conditions, allowing the system to adapt between high destage frequency (when cache is full) and low destage frequency (when cache has space), thereby resolving the contradiction between cache availability and foreground throughput

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

A feedback mechanism is implemented where the throttle controller monitors cache usage metrics and uses this information to regulate destage operations. The controller receives feedback about cache state and adjusts destage frequency accordingly, preventing destage from running at maximum frequency continuously and thus protecting foreground I/O performance while ensuring cache space availability when needed

Inventive Principle:
Principle #23Feedback

2Reliability

If destaging runs frequently to maintain cache space, then write pending state is reduced, but write time increases due to processor resource diversion

Engineering Contradiction:
Improvewrite completion reliabilityVSAvoidwrite time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adjusts destage frequency based on real-time cache usage rather than running at constant high frequency. This dynamic control ensures destaging occurs frequently enough to prevent write pending states (maintaining reliability) but not so frequently that it consistently diverts processor resources from foreground writes (reducing time loss)

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If destage frequency is increased to match user I/O rates, then cache space is maintained, but processor bandwidth for foreground processing is reduced

Engineering Contradiction:
Improveadaptability to user I/O ratesVSAvoidprocessor bandwidth consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

Destage frequency is dynamically adjusted to match user I/O rates rather than running at fixed maximum frequency. The throttle controller monitors the actual I/O rate and scales destage frequency proportionally, maintaining adaptability to varying workloads while preventing excessive processor bandwidth consumption that would harm foreground performance

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of destage based on monitored conditions. When user I/O rates are high, destage frequency increases to maintain cache space; when I/O rates are low, destage frequency decreases to conserve processor bandwidth. This parameter adjustment resolves the contradiction between adaptability and resource consumption

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20200409596A1I/O destaging bandwidth control
Publication Date: 2020.12.31 VMWARE INC
  • US20200409596A1 patent drawing
  • US20200409596A1 patent drawing
  • US20200409596A1 patent drawing

AI summary

Destaging data from a first tier data store to a second tier data store can be performed periodically and concurrently while processing user I/O operations. Each round of destaging can be delayed by certain amount (sleep time). A throttling factor can be used to compute the sleep time as a fraction of a base sleep time. The throttling factor can vary based on the usage level of first tier data store, and can be used to determine the destage frequency.