I/O Device Modes for Memory Pools and Predictable WCET
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Solution Overview
Problem
In time-partitioned safety-critical systems, determining Worst-Case Execution Time (WCET) is challenging due to timing non-determinism caused by memory interference from sources like processor cores, DMAs, GPUs, and specialized co-processors, especially when interacting with I/O devices that require physically contiguous memory regions incompatible with memory pools.
Innovation Solution
The system partitions CPU cache and main memory into dedicated pools for applications and I/O devices, using non-contiguous memory locations aligned with cache partitions to minimize cache interference, allowing I/O devices to operate in linked-list descriptor mode or with specialized hardware/software to respect memory pools, ensuring fast cached accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory is partitioned into pools for safety-critical applications, then cache interference is reduced and WCET becomes more predictable, but I/O devices cannot access physically contiguous memory regions
Solution Approach 1:
The patent introduces an I/O device interface that acts as an intermediary between I/O devices and the memory pool system. This interface translates I/O device requests for physically contiguous memory into accesses of non-contiguous memory locations within the appropriate memory pool, allowing I/O devices to operate without direct access to contiguous memory while maintaining pool isolation.
Solution Approach 2:
The patent segments memory into distinct pools with unique characteristics, allowing different portions of memory to serve different purposes. I/O device memory is segmented as a separate pool that is isolated from application memory pools, enabling independent management and access patterns for I/O operations while maintaining overall system isolation.
2Ease of manufacture
If I/O devices use physically contiguous memory regions, then memory allocation is simplified, but cache interference increases and WCET becomes unpredictable
Solution Approach 1:
The memory pool interface serves as an intermediary that handles memory allocation for I/O devices without requiring physically contiguous regions. It manages the mapping between I/O device logical addresses and physical non-contiguous locations within the I/O memory pool, simplifying allocation while preventing cache interference.
Solution Approach 2:
The patent applies different memory allocation qualities to different memory pools. Application memory pools use non-contiguous allocation optimized for cache performance, while I/O memory pool uses allocation patterns optimized for I/O device requirements. Each pool has its own access rules and characteristics tailored to its specific use case.
3Reliability
If memory pools use non-contiguous memory locations, then cache interference between applications is minimized, but I/O device access complexity increases
Solution Approach 1:
The I/O device interface and memory pool manager act as intermediaries that handle the complexity of non-contiguous memory access. They provide a simplified interface to I/O devices while managing the underlying non-contiguous memory structure, translating device requests into appropriate memory pool accesses without exposing complexity to the device.
Solution Approach 2:
The system creates and maintains descriptor structures that copy and represent the logical view of memory for I/O devices. These descriptors contain the mapping information between logical I/O addresses and physical non-contiguous locations, allowing the interface to manage complexity through data structures rather than complex hardware logic.
Data Source
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AI summary
Examples of computing systems that include input/output (I/O) devices that respect an existing hardware resource partitioning in a modern computing platform are provided.