IO DMA Controller Grouping for Legacy Device Data Transfer
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Solution Overview
Problem
Legacy IO devices without embedded DMA controllers require the processor to perform repetitive and sequential data transfers, leading to inefficiencies and increased processor idle time, especially in systems with high-frequency processors that operate under loosely ordered memory models, where strictly ordered access is necessary for IO devices.
Innovation Solution
An IO direct memory access controller assigns IO devices to groups for sequential access, using a memory access request format with an IO group identification tag, time delay, and command to perform direct memory access in a predetermined order, allowing for efficient and in-order data transfer without processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor performs sequential data transfers for legacy IO devices, then data transfer can be completed, but processor cycles are wasted and processing speed decreases
Solution Approach 1:
The patent extracts the data transfer function from the processor by introducing a separate DMA controller that handles all data transfer operations between memory and IO devices. This allows the processor to be freed from repetitive load/store operations while the DMA controller independently manages data movement, resolving the contradiction between completing data transfers and avoiding processor time loss.
Solution Approach 2:
The DMA controller serves as an intermediary between the processor and legacy IO devices. It translates the processor's high-level commands into the sequential register accesses required by legacy devices, while maintaining the appearance of direct processor control. This mediator enables efficient DMA operation while ensuring compatibility with devices that require strictly ordered access.
2Speed
If the processor operates under loosely ordered memory model, then processing speed increases, but strict ordering required by IO devices cannot be ensured
Solution Approach 1:
The patent segments the memory access operations into two distinct paths: one for general processor operations that can utilize loose ordering for speed, and another for IO device communications that enforce strict ordering through the DMA controller. The DMA controller maintains separate command queues and execution streams for IO operations, ensuring that memory accesses to IO devices occur in the required sequential order while the processor continues at high speed with relaxed ordering for other operations.
Data Source
AI summary
Direct memory access is provided for each member of a group of IO devices organized into groups. Direct memory access for each IO device is performed in a predetermined order based on the predetermined groups, and may be completed by notification by an interrupt request. A predetermined time delay may be specified between each memory access by each IO device of a predetermined group.