Dynamic Gate Biasing in I/O Drivers for Over-Voltage Protection
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Solution Overview
Problem
Existing I/O drivers face challenges in using lower voltage devices while maintaining reliability, as they are exposed to voltages exceeding their reliability limits, leading to potential damage due to negative bias temperature instability and hot carrier injection.
Innovation Solution
The implementation of a dynamic gate biasing system for I/O drivers, which includes a pull-up and pull-down circuit with bias voltage generators that adjust voltages across transistors to prevent over-voltage conditions, ensuring that the maximum voltages across devices remain below their reliability limits during transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If I/O drivers use larger FETs to withstand higher voltages, then voltage withstand capability is improved, but manufacturing complexity and cost increase due to requiring different masks and processes
Solution Approach 1:
The I/O driver circuit is segmented into multiple stages with different voltage domains. Buffer transistors are separated into first buffer transistors operating at core voltage and second buffer transistors operating at I/O voltage, allowing each segment to use appropriately sized FETs for its voltage level rather than requiring all FETs to be large enough for maximum voltage
Solution Approach 2:
Different voltage domains are assigned to different parts of the circuit. The first voltage domain (core voltage) uses smaller FETs while the second voltage domain (I/O voltage) uses larger FETs only where needed. This local differentiation allows optimal FET sizing in each region rather than uniform oversized FETs throughout
2Adaptability or versatility
If I/O drivers expose transistors to voltages exceeding reliability limits, then voltage swing range is improved, but transistor reliability deteriorates due to negative bias temperature instability and hot carrier injection
Solution Approach 1:
Bias voltage generators pre-adjust the gate voltages of buffer transistors before voltage transitions occur. During output voltage transitions, the bias voltages are dynamically adjusted in advance to ensure that voltage differences across transistor terminals remain within safe operating limits, preventing reliability degradation before it can occur
Solution Approach 2:
The gate bias voltages are made dynamic rather than fixed. Bias voltage generators continuously adjust the bias voltages applied to buffer transistor gates based on the current output voltage state and transition direction, allowing the circuit to adaptively maintain safe voltage differences across transistors throughout the entire voltage swing range
Data Source
Figure 1A
Figure 1B~1C
Figure 2A
AI summary
An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.