I/O Driver Full-Gate Boosting for Fast, Reliable MOSFET Switching
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Solution Overview
Problem
Existing input/output (I/O) drivers face reliability issues due to excessive voltage stresses on transistors during signal transitions, leading to potential damage from negative bias temperature instability (NBTI) and hot carrier injection (HCI), especially when operating beyond the 1.3V reliability limit.
Innovation Solution
The implementation of a dynamic full-gate boosting technique for both pull-up and pull-down transistors, where control signals are dynamically adjusted to keep the voltage across transistors below their reliability limits during transitions, using predrivers to generate boosted voltages and manage transistor resistances for faster and safer switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistors are operated at high voltage to improve switching speed, then switching speed is improved, but transistor reliability deteriorates due to excessive voltage stress causing NBTI and HCI damage
Solution Approach 1:
The patent implements dynamic voltage control by adjusting the gate voltage of the second transistor based on the operating state (steady-state vs. transition). During transitions, the gate voltage is boosted to increase switching speed, while during steady-state operation, the gate voltage is reduced to minimize voltage stress and prevent NBTI/HCI damage. This dynamic adjustment resolves the contradiction between speed and reliability.
Solution Approach 2:
The patent changes the voltage parameter dynamically by using different gate voltages for different operating conditions. The gate voltage of the second transistor is changed from a standard voltage (e.g., 0.9V) during steady-state to a boosted voltage (e.g., 1.8V) during transitions. This parameter change allows the system to achieve high switching speed when needed while maintaining transistor reliability during normal operation.
2Loss of time
If voltage stress is increased to reduce transition time, then transition speed is improved, but transistor damage risk increases due to NBTI and hot carrier injection
Solution Approach 1:
The patent applies periodic voltage boosting only during the brief transition periods rather than continuously. The gate voltage of the second transistor is boosted to a higher level (e.g., 1.8V) only when transitioning between logic states, and returns to a lower level (e.g., 0.9V) during steady-state operation. This periodic action reduces the cumulative exposure to high voltage stress, minimizing NBTI and HCI damage while achieving fast transitions when needed.
Solution Approach 2:
The patent applies preliminary voltage boosting to the gate of the second transistor before the actual switching transition occurs. The control circuit detects the transition state and proactively increases the gate voltage to prepare the transistor for rapid switching. This preliminary action ensures that the transistor is ready to switch quickly while limiting the duration of high voltage exposure, thereby reducing damage risk.
3Device complexity
If standard voltage control is used to simplify circuit design, then device complexity is reduced, but switching performance deteriorates due to inability to dynamically optimize transistor operation
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the input signal and the second transistor's gate. This control circuit monitors the operating state and dynamically adjusts the gate voltage accordingly. While this adds some complexity, it enables optimal switching performance by boosting the gate voltage during transitions and reducing it during steady-state, thereby resolving the contradiction between simplicity and performance.
Data Source
AI summary
An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.