IO Expander Channel Switching for Memory Subsystems
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Solution Overview
Problem
Previous input/output (IO) expander devices in memory sub-systems face challenges in efficiently managing channel switching, leading to decreased load capability as more NAND dies are added, and potential malfunctions due to unfiltered headers.
Innovation Solution
The implementation of a channel switching component in the IO expander device that can switch channels in response to receiving a header, allowing the header to pass through a first channel while the payload is sent through a second channel, thereby preventing headers from affecting the memory resource.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more NAND dies are added to the memory sub-system, then the storage capacity is increased, but the load capability decreases due to inefficient channel switching management
Solution Approach 1:
The patent implements dynamic channel switching in the IO expander device, allowing the system to dynamically route headers and payloads through different channels based on real-time conditions. This dynamic management enables efficient load distribution across multiple NAND dies, maintaining high load capability even as storage capacity increases through additional dies.
2Productivity
If channel switching is implemented in the IO expander device, then the load capability is enhanced, but the device complexity increases
Solution Approach 1:
The patent segments the channel switching function into distinct components within the IO expander device: a channel switcher module that handles header routing and a separate payload routing mechanism. This segmentation allows each component to perform its specific function independently, managing complexity while enabling enhanced load capability through coordinated operation.
Solution Approach 2:
The IO expander device acts as an intermediary between the host system and multiple NAND dies, centralizing the channel switching logic in this intermediate component. This intermediary approach consolidates complexity in a single device rather than distributing it across multiple components, making the system more manageable while achieving high load capability.
3Device complexity
If headers are allowed to pass through the same channel as payloads, then the device complexity is reduced, but potential malfunctions occur due to unfiltered headers affecting memory resources
Solution Approach 1:
The patent segments the transmission path into separate channels for headers and payloads within the IO expander device. The channel switcher specifically routes headers through one channel while directing payloads through another, preventing headers from affecting memory resources while maintaining simple device architecture.
Solution Approach 2:
The patent extracts headers from the payload transmission path by implementing separate routing for header and payload signals. This extraction ensures that headers are processed independently and cannot interfere with memory operations, improving reliability without significantly increasing device complexity.
Data Source
AI summary
A method includes receiving, by a memory device interface, a signal from a host that includes a header, decoding, by the memory device interface, the header to determine an instruction, selecting, by the memory device interface, a first channel associated with a first memory resource based on the instruction, sending, by the memory device interface, the header to a second channel associated with a second memory resource, and sending, by the memory device interface, subsequent packets of the header to the first channel.