I/O Hub CRC Control Element for Error Handling

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Solution Overview

Problem

Existing PCIe communication protocols lack efficient end-to-end data protection mechanisms, particularly for FICON and other protocols like T11 and T10 DIF, as they rely on offloading checksums to adapters, which are far from the application and impose performance and CPU utilization penalties, and not all adapters support protocols like FICON CRC.

Innovation Solution

A system and method that utilizes an I/O hub to associate a CRC control element with I/O operations, updating it to indicate error states and block incomplete requests while allowing other operations to continue, enabling hardware-based CRC generation and checking closer to the application without performance impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If checksum offloading is provided in the adapter, then data protection is improved, but the checking is further from the application and performance penalties occur

Engineering Contradiction:
Improvedata protectionVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces an intermediary CRC control element that mediates between the adapter and memory, enabling CRC checking to be performed at the I/O hub level rather than solely at the adapter level. This intermediary structure allows the system to achieve both data protection and performance efficiency by positioning the checking mechanism closer to the application while maintaining hardware-based offloading.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent adds a new dimensional layer to the existing data protection architecture by introducing CRC control elements at the I/O hub level, rather than only at the adapter level. This dimensional expansion allows the system to perform checking at multiple levels simultaneously, achieving both proximity to application and hardware-based performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If software generation and checking is used, then checking is closest to the application, but performance and CPU utilization penalties occur

Engineering Contradiction:
Improvedata protectionVSAvoidCPU utilization
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces the mechanical software-based checking system with a hardware-based CRC generation and checking mechanism implemented in the I/O hub. This substitution eliminates CPU involvement in CRC operations, achieving both application-level checking proximity and reduced CPU utilization through hardware automation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The I/O hub performs CRC generation and checking autonomously through hardware-based control elements without requiring CPU intervention. The system serves itself by implementing self-checking capabilities at the I/O hub level, achieving both application-proximity checking and reduced CPU utilization penalties.

Inventive Principle:
Principle #25Self-service

3Reliability

If error blocking is applied to all I/O requests, then data integrity is improved, but productivity of other operations deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidconcurrent I/O operations
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the error handling mechanism to operate at the individual I/O operation level rather than at the adapter level. Each I/O operation has its own control element that can be independently blocked upon error detection, allowing other concurrent operations to continue unaffected. This segmentation maintains data integrity for erroneous operations while preserving productivity of healthy operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies error blocking locally to specific I/O operations that encounter errors, rather than globally to all operations. The control element associated with the erroneous I/O operation is selectively blocked, while other operations maintain normal execution. This localized error handling preserves both data integrity and concurrent operation productivity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9354967B1I/O operation-level error-handling
Publication Date: 2016.05.31 CAPROCK INTEGRATED TECHNOLOGIES LLC
  • US9354967B1 patent drawing
  • US9354967B1 patent drawing
  • US9354967B1 patent drawing

AI summary

Error-handling in a computing environment at an input/output (I/O) level is facilitated by associating a control element with an input/output (I/O) operation based on a command to perform the I/O operation between an adapter and memory. Based on detection of an error for the I/O operation, the control element is updated to indicate an error state, and completion of any uncompleted I/O request for the I/O operation is blocked, while other I/O requests for one or more other I/O operations are allowed to proceed between the adapter (or adapter function) and the memory. By way of example, the control element may be a cyclic redundancy check (CRC) control element used, for instance, by an I/O hub of the computing environment to accumulate during performance of the I/O operation an accumulated CRC value for the I/O operation to facilitate error checking of the operation.