I/O Hub Power State Management for Latency Control

Solution Overview

Problem

Current computer systems face challenges in managing power states for processor and I/O servicing components, leading to increased interrupt latency and performance degradation due to deeper power states requiring longer transition times, which negatively impact user experience, especially in applications sensitive to real-time performance.

Innovation Solution

A method is introduced where the I/O servicing component, such as an input-output hub, adjusts its power states based on the processor's present power state, establishing a servicing power state floor that corresponds to the processor's power state, thereby ensuring the I/O servicing component operates within allowable power states that balance power savings and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the I/O servicing component operates in a deeper power state to save power, then power consumption is reduced, but interrupt latency increases and system performance deteriorates

Engineering Contradiction:
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The I/O servicing component dynamically adjusts its power state based on the processor's current power state and activity requirements. The component transitions between different power states (C0-Cn) in real-time, selecting the appropriate depth based on whether the processor is active or in a low-power state, thereby optimizing the balance between power savings and interrupt latency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by adjusting the I/O servicing component's power state floor according to the processor's power state. When the processor is in a deeper power state, the I/O component is allowed to operate at deeper power states; when the processor is active, the I/O component maintains shallower power states to ensure low interrupt latency

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If the I/O servicing component enters a deeper power state, then power savings increase, but transition time to resume operation increases

Engineering Contradiction:
Core Design Contradiction:
Loss of energyVSDuration of action of moving object

Solution Approach 1:

The I/O servicing component anticipates the processor's power state transitions and adjusts its own power state accordingly. By monitoring the processor's power state and proactively transitioning to appropriate power states, the I/O component avoids unnecessary deep transitions when the processor is active, thereby reducing overall transition time while maintaining power savings during processor idle periods

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If the I/O servicing component operates independently from the processor power state, then component autonomy is maintained, but system-wide power optimization is reduced

Engineering Contradiction:
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The I/O servicing component implements feedback mechanisms by monitoring the processor's power state and using this information to adjust its own power state floor. This feedback loop allows the I/O component to maintain operational autonomy while simultaneously optimizing system-wide power consumption based on the processor's current state and activity requirements

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8862920B2Power state management of an input/output servicing component of a processor system
Publication Date: 2014.10.14
  • US8862920B2 patent drawing
  • US8862920B2 patent drawing
  • US8862920B2 patent drawing

AI summary

A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state.