IO Interface Hold Circuit for Stable Partial Reconfiguration

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Solution Overview

Problem

Partial reconfiguration of programmable logic devices often leads to unstable external input/output (IO) interfaces, as existing systems cannot reconfigure IO interfaces, resulting in unpredictable performance.

Innovation Solution

A circuit and method that stabilize IO interfaces by using a selection circuit and control circuit to hold input/output ports at predetermined values during partial reconfiguration, allowing for synchronous or asynchronous switching of values using existing clocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If partial reconfiguration is performed on programmable logic devices, then device adaptability and reconfigurability are improved, but IO interface stability deteriorates

Engineering Contradiction:
ImprovereconfigurabilityVSAvoidIO interface stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides the reconfiguration process into segments by introducing a hold state for specific IO interfaces. The IO interface is segmented into configurable portions and fixed hold portions, allowing partial reconfiguration of logic blocks while maintaining stability of external interfaces through the hold state mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-establishing hold states for IO interfaces before reconfiguration occurs. The control circuit is configured to enter the hold state in advance during reconfiguration transitions, ensuring IO stability is maintained before the reconfiguration process begins, thus preventing instability issues.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If IO interfaces remain fixed during partial reconfiguration, then IO interface stability is maintained, but system functionality and adaptability are limited

Engineering Contradiction:
ImproveIO interface stabilityVSAvoidsystem functionality
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic control of IO interfaces through a controllable hold state. The IO interface can dynamically transition between normal operation mode and hold state based on reconfiguration needs. This dynamic mechanism allows the system to maintain stability when required while enabling reconfiguration functionality, resolving the contradiction between fixed stability and adaptive flexibility.

Inventive Principle:
Principle #15Dynamics

3Reliability

If decoupling logic is added to maintain IO stability during reconfiguration, then IO interface stability is improved, but device complexity increases

Engineering Contradiction:
ImproveIO interface stabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the hold state control functionality directly into the IO interface circuitry itself, combining multiple functions (normal operation, hold state, and control logic) into a unified interface structure. This integration eliminates the need for separate decoupling logic circuits, maintaining IO stability while avoiding additional circuit complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The IO interface circuit is designed with multi-functionality, serving both normal operation and hold state functions within the same circuit structure. The universal interface can operate in different modes (normal or hold) based on control signals, eliminating the need for dedicated decoupling logic and reducing overall device complexity while maintaining stability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10541686B1Circuit and method for ensuring a stable IO interface during partial reconfiguration of a reprogrammable integrated circuit device
Publication Date: 2020.01.21 XILINX INC
  • US10541686B1 patent drawing
  • US10541686B1 patent drawing
  • US10541686B1 patent drawing

AI summary

A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.