Interrupt Coalescing for I/O Completions in Virtualized Systems

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Solution Overview

Problem

In virtualized computer systems, the high overhead of handling I/O completion interrupts leads to CPU resource shortages, particularly during high I/O rates, due to the inefficiency of existing interrupt coalescing techniques that rely on fine-grained timers, which are difficult to implement and inefficient in virtualization logic.

Innovation Solution

A method that records delivery times for I/O completion interrupts and determines whether a selected period has elapsed since the last inter-processor interrupt, delivering an interrupt only when the period has elapsed, thereby coalescing multiple I/O completions into a single interrupt and reducing CPU overhead without relying on high resolution timers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If interrupt coalescing is implemented using fine-grained timers, then interrupt delivery timing can be controlled, but the device complexity and implementation difficulty increase significantly

Engineering Contradiction:
Improveinterrupt delivery timing controlVSAvoidfine-grained timer implementation
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent extracts the timing control functionality from complex fine-grained timers and implements it using simpler software-based timestamp recording and comparison. Instead of hardware timers, the system records delivery timestamps in software and compares them against a selected period threshold, achieving timing control without the complexity of fine-grained timer hardware.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/hardware-based fine-grained timer system with a software-based timestamp comparison mechanism. This substitution eliminates the need for complex timer hardware while achieving the same timing control objective through software logic that records timestamps and compares intervals.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If multiple I/O completion interrupts are handled individually, then each completion is processed immediately, but CPU overhead increases significantly during high I/O rates

Engineering Contradiction:
ImproveI/O completion processing speedVSAvoidCPU overhead
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges multiple individual I/O completion interrupts into a single coalesced interrupt by tracking the timestamp of the last interrupt delivery and comparing it against a selected period. When multiple completions occur within the selected period, they are combined into one interrupt event, reducing the total number of interrupt handling operations and thereby reducing CPU overhead during high I/O rates.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If interrupt coalescing delays interrupt delivery to reduce CPU overhead, then CPU efficiency improves, but I/O latency increases

Engineering Contradiction:
ImproveCPU efficiencyVSAvoidI/O latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic interrupt coalescing by adjusting the selected period threshold based on system conditions. The system can adaptively modify the coalescing threshold to balance between reducing CPU overhead and minimizing I/O latency, allowing the interrupt delivery timing to be optimized dynamically rather than using a fixed threshold.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9336165B2Interrupt coalescing for outstanding input/output completions
Publication Date: 2016.05.10 VMWARE INC
  • US9336165B2 patent drawing
  • US9336165B2 patent drawing
  • US9336165B2 patent drawing

AI summary

In a computer system, a method of controls interrupts which correspond to input/output (I/O) processing. For each delivery of an I/O completion interrupt, the method provides a recordation of a delivery time; identifies I/O completions for which deliveries of corresponding I/O completion interrupts involve deliveries of inter-processor interrupts; and for each of the identified I/O completions, accesses the recordation of the most recent delivery time to determine whether a selected period of time has elapsed since a last delivery of an inter-processor interrupt. As a response to a determination that the selected period has elapsed, an inter-processor interrupt is delivers. As a response to a determination that less than the duration of the selected period has elapsed, the method refrains from delivering an inter-processor interrupt.