I/O Keeper Cell Wake-Up Control for Low-Power State Retention
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Solution Overview
Problem
Current low power mode exit mechanisms in integrated circuit devices reset I/O control and data states, potentially disturbing other devices in an electronic system, as they revert to default states upon waking from low power mode.
Innovation Solution
Implementing a 'low power mode wake-up and restore' signal to control I/O keeper cells, allowing them to maintain and restore the previous I/O configuration and data states when the device exits low power mode, ensuring seamless interaction with other devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the integrated circuit device exits low power mode by performing a power-on reset (POR), then internal logic states are restored, but I/O control and data states are reset to default states which disturbs other devices in the electronic system
Solution Approach 1:
The patent segments the state restoration process by separating internal logic circuit restoration from I/O state restoration. Internal logic circuits undergo POR to restore their states, while I/O keeper cells are excluded from this reset process, allowing them to maintain previous I/O control and data states. This segmentation resolves the contradiction by enabling internal state restoration without forcing I/O states into default configurations that would disturb external devices.
Solution Approach 2:
The patent extracts the I/O keeper cells from the standard POR process. During exit from low power mode, while most of the device undergoes reset, the I/O keeper cells are taken out of this reset process and maintain their previously stored I/O states. This extraction allows the I/O interface to remain stable and consistent with external devices while the internal logic is restored.
2Stability of the object's composition
If standard I/O keeper cells are used to retain I/O control and data states during low power mode, then I/O states are maintained, but upon waking from low power mode the states are reset to default states
Solution Approach 1:
The patent applies preliminary action by having I/O keeper cells store and hold the I/O control and data states before the device enters low power mode. These keeper cells are pre-configured to maintain these states throughout the low power period and are designed to resist the reset signal that affects other circuits. This preliminary state capture ensures that when the device wakes up, the I/O states are already prepared and protected from reset.
Solution Approach 2:
The patent introduces dynamic control through a wake-up signal that selectively manages the I/O keeper cells. The keeper cells transition from a holding state during low power mode to a release state upon receiving the wake-up signal, at which point they transfer control back to the logic circuits. This dynamic behavior allows the system to adapt the I/O state management based on the power mode, maintaining stability during low power and enabling proper operation upon wake-up.
Data Source
AI summary
A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.