IO Level Shift Circuit Using Intermediate Vdd_io Generation
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Solution Overview
Problem
Conventional IO interface circuits face challenges such as high cost, difficult realization, high power consumption, and limited application range due to the need for additional pins and complex power supply generation for level shifting, which complicates chip design and increases standby power consumption.
Innovation Solution
A level shift circuit for IO interfaces is proposed, comprising an intermediate level generation sub-circuit and a level shift sub-circuit, utilizing a current mirror unit and intermediate level generation unit to provide an intermediate level Vdd_io, allowing for level shifting without requiring an external power domain or additional power generation, thus reducing costs and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the interface level of the Host is introduced to the inside of the chip for level shift with internal power supply, then level shifting function is achieved, but additional pin is required which increases chip cost and degrades competitiveness
Solution Approach 1:
The patent extracts the level shifting function from the external Host interface level introduction and relocates it to an internal LDO-based power supply generation system. By generating the external interface power supply internally through the LDO circuit, the need for additional external pins is eliminated, thus resolving the contradiction between achieving level shifting and reducing pin count.
Solution Approach 2:
The patent introduces an LDO (Low Dropout Regulator) as an intermediary component that converts the internal power supply to the required external interface voltage level. This intermediary power supply generation mechanism enables level shifting without directly introducing external Host levels, thereby avoiding the need for additional pins while maintaining the level shifting capability.
2Ease of manufacture
If level shift is realized by generating external interface power supply through internal LDO, then level shifting is achieved, but reference voltage and reference current must be generated simultaneously which increases circuit complexity and standby power consumption
Solution Approach 1:
The patent merges the reference voltage generation and reference current generation functions into a single integrated LDO circuit structure. By combining these functions, the circuit avoids the complexity of separate generation paths while maintaining the ability to provide both reference voltage and reference current simultaneously, thus reducing overall circuit complexity and standby power consumption.
3Ease of manufacture
If level shift is realized by generating external interface power supply through internal LDO, then level shifting is achieved, but standby power consumption increases
Solution Approach 1:
The patent implements periodic or on-demand activation of the LDO circuit based on operational requirements. The LDO is activated only when level shifting is needed and can be put into a low-power or standby state when not in use, thereby reducing overall standby power consumption while maintaining the level shifting capability when required.
Data Source
Figure 1~2
Figure 3
AI summary
Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.