IO Level Shifter Circuit With Diode Stacks for Flexible Output Voltage
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Solution Overview
Problem
Integrated circuits face challenges in reducing power consumption and enhancing performance per unit area due to voltage differences between core logic and IO interfaces, requiring efficient level shifting with low power supply voltage and high voltage output within specific ranges, while avoiding complex bias circuits.
Innovation Solution
A level shifter architecture incorporating dynamic biasing and diode-connected devices to generate flexible output voltages, using pull-up and pull-down circuits with diode stacks to adjust voltage levels and prevent electrical overstress, allowing for configurable VOH and VOL within the desired ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level shifting is used to accommodate voltage differences from core logic to IO interfaces, then voltage compatibility is improved, but power consumption increases and performance per unit area decreases
Solution Approach 1:
The patent changes the voltage parameters dynamically by using different transistor threshold voltages (Vt) to achieve different output voltage levels (VOH and VOL). By selecting transistors with appropriate Vt values, the level shifter can adapt to different voltage requirements while maintaining low power consumption and high performance per unit area.
2Adaptability or versatility
If VOH is increased to be higher than 0.8 times Vddhi, then voltage output range is improved, but power consumption increases
Solution Approach 1:
The patent achieves different VOH levels (higher or lower than 0.8 times Vddhi) by changing the threshold voltage parameter of the pull-up transistor. This allows the output voltage range to be adjusted according to requirements without increasing power consumption, as the transistor sizing and Vt selection optimize the power-voltage tradeoff.
3Adaptability or versatility
If VOL is decreased to be lower than 0.2 times Vddhi, then voltage output range is improved, but power consumption increases
Solution Approach 1:
The patent controls VOL levels (higher or lower than 0.2 times Vddhi) by adjusting the threshold voltage parameter of the pull-down transistor. This enables flexible voltage output range adjustment while maintaining low power consumption through optimized transistor selection and sizing.
4Stability of the object's composition
If complex bias circuits are used to provide constant bias, then voltage stability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex bias circuits from the level shifter design. Instead of using traditional constant bias circuits, the invention relies on transistor threshold voltage selection and sizing to achieve stable voltage levels, thereby reducing device complexity while maintaining voltage stability.
5Use of energy by moving object
If transistor sizing is optimized for low power, then power consumption is reduced, but voltage output precision may be affected
Solution Approach 1:
The patent achieves both low power consumption and precise voltage output by changing the threshold voltage parameter (Vt) of transistors rather than relying solely on transistor sizing. By selecting transistors with appropriate Vt values, the design achieves accurate VOH and VOL levels while maintaining optimized power consumption through appropriate device sizing.
Data Source
AI summary
An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level.