Multi-Port IO-Link Master Transceiver With Reconfigurable DIO Pins
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Solution Overview
Problem
Current IO-Link master devices require additional components and external drivers to support 8-port master transceivers, lacking flexibility for digital input/output (DIO) functionality and increasing the number of external parts and interfaces.
Innovation Solution
A reconfigurable integrated circuit system combining IO-Link master functionality with DIO capabilities, utilizing a microcontroller unit (MCU) and daisy-chained reconfigurable devices with SPI protocol, enabling flexible configuration of pin sets for IO-Link and DIO modes, and integrating SPI interface for communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional components and external drivers are used to support 8-port master transceiver, then IO-Link functionality is achieved, but device complexity and component count increase
Solution Approach 1:
The patent combines IO-Link master transceiver functionality and digital input/output (DIO) capabilities into a single integrated reconfigurable device. This merging eliminates the need for separate transceiver chips and external drivers, reducing component count while maintaining full IO-Link functionality across 8 ports.
Solution Approach 2:
The reconfigurable device is designed to perform multiple functions: it can operate as an 8-port IO-Link master transceiver, as digital input/output channels, or in hybrid configurations. Each pin set can be dynamically configured for different modes, making the device universal and adaptable to various application requirements without needing additional components.
2Adaptability or versatility
If separate transceiver chips are used for 8-port output, then IO-Link communication is enabled, but the number of external parts and interfaces increases
Solution Approach 1:
The patent integrates eight IO-Link transceiver channels into a single reconfigurable device rather than using eight separate transceiver chips. This consolidation reduces the quantity of external parts while maintaining the ability to support 8-port IO-Link communication simultaneously or in configurable combinations.
Solution Approach 2:
The single reconfigurable device provides universal transceiver functionality that can operate in multiple configurations: all 8 ports as IO-Link channels, all ports as DIO channels, or any combination thereof. This eliminates the need for multiple specialized chips and reduces the overall number of external components required.
3Reliability
If dedicated IO-Link master devices are used, then IO-Link protocol support is achieved, but flexibility for DIO functionality is lost
Solution Approach 1:
The reconfigurable device employs dynamic configuration capability where each pin set can be programmed and switched between IO-Link mode and DIO mode at runtime. This dynamic adaptability allows the system to reliably support IO-Link protocol when needed while simultaneously providing flexible DIO functionality, resolving the contradiction between protocol reliability and functional versatility.
Solution Approach 2:
The device is designed as a universal platform that natively supports both IO-Link master protocol and digital input/output operations. The same hardware resources can be allocated to different functions based on system requirements, providing both reliable protocol support and flexible DIO capability without compromise.
Data Source
AI summary
Disclosed herein is a system, including a microcontroller unit (MCU) and a plurality of reconfigurable devices connected to the MCU in a daisy chain arrangement via a Serial Peripheral Interface (SPI) protocol. Each reconfigurable device includes control circuitry configured for operating in both a Digital Input/Output (DIO) mode and an IO-Link mode, a digital logic for switching the DIO control circuitry between the DIO mode and the IO-Link mode, output drivers connected between outputs of the control circuitry and respective output pins of a plurality of pin sets, input filters connected between inputs of the control circuitry and respective inputs pins of the plurality of pin sets, and an SPI interface for communication with the MCU and other reconfigurable devices in the daisy chain, with the digital control facilitating communication between the SPI interface and the control circuitry.