Integrated I/O Lockstep Processing for ASIL-D Safety

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current systems for achieving ASIL-D safety level in ADAS applications are costly due to the need for redundant CPU components, and there is a lack of effective solutions for ensuring high reliability in integrated I/O processing, which is critical for safety but increases hardware complexity and expense.

Innovation Solution

An integrated I/O processing system with a tightly coupled I/O lockstep configuration within a single CPU, utilizing two redundant I/O stacks that process data in parallel and compare outputs to detect faults, reducing the likelihood of failure and achieving high reliability without the need for multiple redundant processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple redundant processors are used to increase I/O accuracy, then reliability is improved, but device complexity and cost increase

Engineering Contradiction:
ImproveI/O accuracyVSAvoidprocessor quantity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges two I/O stacks within a single processor, integrating redundant processing functionality into one device rather than using separate processors. This reduces device complexity while maintaining the reliability benefits of redundancy through the integrated first and second I/O stacks that process data simultaneously

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a redundant copy of the I/O processing logic by implementing both a first I/O stack and a second I/O stack within the same processor. These stacks independently process the same I/O data, providing redundancy for accuracy verification without requiring additional physical processors

Inventive Principle:
Principle #26Copying

2Reliability

If multiple redundant processors are used to increase I/O accuracy, then reliability is improved, but cost increases

Engineering Contradiction:
ImproveI/O accuracyVSAvoidprocessor quantity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple I/O stacks into a single processor unit, reducing the total quantity of processors needed. The first I/O stack and second I/O stack coexist within one processor, eliminating the need for multiple separate processor components while maintaining redundant processing capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single processor is designed to perform multiple functions by hosting both the first I/O stack and second I/O stack simultaneously. This multi-functional design allows one processor to replace what would traditionally require multiple specialized processors, reducing overall system cost

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If integrated I/O processing with redundant stacks is implemented, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvefailure rateVSAvoidI/O stack configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent integrates multiple I/O stacks within a single processor device, consolidating complexity into one unified component rather than distributing it across multiple devices. The first I/O stack and second I/O stack are merged into the same processor, simplifying system architecture while maintaining redundancy

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The processor acts as an intermediary that manages the complexity of multiple I/O stacks internally while presenting a simplified interface to the rest of the system. The processor handles the coordination between first and second I/O stacks, shielding external components from the underlying complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10860515B2Integrated input/output management
Publication Date: 2020.12.08 INTEL CORP
  • US10860515B2 patent drawing
  • US10860515B2 patent drawing
  • US10860515B2 patent drawing

AI summary

Herein is disclosed an integrated input/output (“I/O”) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.