I/O Logic Virtual Address Translation for Image Forming Apparatus
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Solution Overview
Problem
Conventional image forming apparatuses face delays in data read and write processes due to the need to translate virtual memory addresses into physical memory addresses, which can result in inefficient data copying and resource waiting due to dispersed memory allocation.
Innovation Solution
An image forming apparatus with a control unit that includes a processor core operating in virtual memory, a main memory for physical memory operations, and I/O logics that utilize a translation look-aside buffer (TLB) to translate virtual memory addresses into physical memory addresses, along with direct memory access (DMA) for efficient data access, and an address prediction unit to optimize TLB updates based on access patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If virtual memory address translation is performed for each data access, then data can be accessed in a virtual address space, but translation delay occurs reducing access speed
Solution Approach 1:
The patent applies preliminary action by predicting future virtual addresses that will be accessed and pre-translating them to physical addresses before actual access occurs. The address prediction unit generates predicted virtual addresses based on access patterns, and these are translated in advance and stored in the TLB, so when the actual access occurs, the translation is already available, eliminating the translation delay.
Solution Approach 2:
The patent implements beforehand cushioning by maintaining a TLB that stores pre-translated virtual-to-physical address mappings. When address translation is needed, the system first checks the TLB for a cached translation, and if found, uses it immediately without performing a full translation. This cushioning mechanism prepares translations in advance and keeps them ready for quick retrieval.
2Productivity
If data is copied through hardware IP core, then data processing can be performed, but physical consecutive space must be allocated causing dual copy overhead
Solution Approach 1:
The patent extracts the address translation function from the general-purpose processor and implements it in dedicated I/O logics that are integrated with the hardware IP cores. This allows the I/O logics to directly translate virtual addresses to physical addresses and access memory without requiring data to be copied through the processor, eliminating the dual copy overhead while maintaining data processing capability.
Solution Approach 2:
The patent introduces I/O logics as intermediaries between the processor and memory system. These I/O logics perform address translation and memory access operations, acting as mediators that handle the conversion from virtual to physical addresses directly at the memory interface level, thereby avoiding the need for data to traverse through the processor for translation purposes.
3Speed
If memory is allocated in physically consecutive space, then hardware can operate efficiently, but memory manager may not ensure such space causing stand-by state
Solution Approach 1:
The patent applies preliminary action by having the address prediction unit continuously generate and translate predicted virtual addresses in advance, preparing physical addresses before they are actually needed. This ensures that when hardware operations require memory access, the corresponding physical addresses are already available in the TLB, eliminating wait states caused by memory allocation issues.
Solution Approach 2:
The patent implements dynamics by making the address translation system adaptive through the address prediction unit, which learns and adapts to access patterns. The prediction mechanism dynamically adjusts which addresses to translate first based on observed usage patterns, allowing the system to optimize for actual access behavior rather than relying on static physical consecutive allocation.
Data Source
AI summary
An image forming apparatus includes a function unit to perform functions of the image forming apparatus, and a control unit to control the function unit to perform the functions of the image forming apparatus. The control unit includes a processor core to operate in a virtual memory address, a main memory to operate in a physical memory address and store data used in the functions of the image forming apparatus, and a plurality of input/output (I/O) logics to operate in the virtual memory address and control at least one of the functions performed by the image forming apparatus. Each of the plurality of I/O logics translates the virtual memory address into the physical memory address corresponding to the virtual memory address and accesses the main memory.