Device-Specific Memory Address Translation via Requestor ID Verification
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Solution Overview
Problem
In computer systems with virtual memory, the global availability of translation information for virtual-to-physical memory address translations compromises system security and stability, as malicious or errant peripheral devices can generate incorrect requests that are indistinguishable from legitimate ones, potentially leading to data corruption or theft.
Innovation Solution
A processor employs device-specific memory address translation by using an I/O memory management unit to verify that the requestor ID in a memory access request matches the ID stored in the I/O memory translation buffer, disallowing access if the IDs do not match and signaling an error condition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If translation information is made globally available to multiple peripheral devices, then memory access efficiency is improved, but system security and stability deteriorate
Solution Approach 1:
The patent segments the translation information access by creating device-specific translation buffers (IO_TLB) for each peripheral device. Each buffer stores translation entries associated with a specific requestor ID, isolating translation information so that only authorized devices can access their designated translations. This segmentation resolves the contradiction by maintaining security through isolation while preserving efficiency through dedicated fast-access buffers for each device.
Solution Approach 2:
The patent implements local quality by associating translation information with specific devices through requestor ID matching. Each translation buffer entry is tagged with a requestor ID, and access is granted only when the requesting device's ID matches the stored ID. This ensures that translation information has different accessibility properties for different devices, improving security while maintaining efficient local access for authorized devices.
2Ease of operation
If translation information is globally available, then ease of operation is improved, but harmful factors increase
Solution Approach 1:
The patent applies preliminary anti-action by implementing requestor ID verification before allowing access to translation information. The IO memory management unit checks whether the requesting device's ID matches the requestor ID stored in the translation buffer entry before permitting memory access. This preventive measure blocks malicious or errant devices from utilizing translation information they should not access, while maintaining convenient access for authorized devices through the same verification mechanism.
Data Source
AI summary
A processor employing device-specific memory address translation. In one embodiment, a processor may include a device interface configured to receive a memory access request from an input/output (I/O) device, where the request specifies a virtual memory address and a first requestor identifier (ID) that identifies the I/O device. The processor may also include an I/O memory management unit coupled to the device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to the virtual memory address is stored within an I/O memory translation buffer. The I/O memory management unit may be further configured to determine whether a second requestor ID stored within the I/O memory translation buffer and corresponding to the memory address translation matches the first requestor ID. If the first and second requestor IDs do not match, the I/O memory management unit may disallow the memory access request and to signal an error condition.